Fujitsu MHW2040AC User Manual

C141-E258-03EN MHW2060AC, MHW2040AC DISK DRIVES PRODUCT MANUAL

This page is intentionally left blank.

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5

5.3 Host Commands (4) WRITE VERIFY (X’3C’) This command operates similarly to the WRITE SECTOR(S) command except that the device verifies each sect

Interface (5) READ VERIFY SECTOR(S) (X’40’ or X’41’) This command operates similarly to the READ SECTOR(S) command except that the data is not tra

5.3 Host Commands (6) SEEK (X’70’ to X’7F’) This command performs a seek operation to the track and selects the head specified in the command block

Interface (7) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device. This command us

5.3 Host Commands Note: The device responds to this command with the result of power-on diagnostic test. At command issuance (I/O registers setting

Interface (8) INITIALIZE DEVICE PARAMETERS (X’91’) The host system can set the number of sectors per track and the maximum head number (maximum he

5.3 Host Commands (9) DOWNLOAD MICROCODE (X’92’) At command issuance (I/O registers setting contents) 1F7h(CM) 1 0 0 1 0 0 1 0 1F6h(DH) 1 X 1

Interface Table 5.5 Operation of DOWNLOAD MICROCODE Host Command Movement of device Subcommand code (FR Reg) Sector count (SN, SC Reg) Data transf

5.3 Host Commands (10) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and ente

Manual Organization MHW2060AC, MHW2040AC DISK DRIVES PRODUCT MANUAL (C141-E258) <This manual> • Device Overview • Device Configuration •

Interface (11) IDLE IMMEDIATE (X’95’ or X’E1’) / UNLOAD IMMEDIATE (X’95’ or X’E1’) • Default function Upon receipt of this command, the device se

5.3 Host Commands Even if the device executes reading look-ahead operation or executes writing operation, the device unloads the head(s) to the ramp

Interface (12) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mo

5.3 Host Commands (13) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2

5.3 Host Commands (14) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confir

Interface Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BS

5.3 Host Commands (16) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR registe

Interface Table 5.7 Features register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART READ DATE: A device that

5.3 Host Commands Table 5.7 Features register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART READ LOG: A devic

This page is intentionally left blank.

Interface Table 5.7 Features register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART RETURN STATUS: When the

5.3 Host Commands At command issuance (I-O registers setting contents) 1F7H(CM) 1 0 1 1 0 0 0 0 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H

Interface Table 5.8 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status fl

5.3 Host Commands • Data format version number The data format version number indicates the version number of the data format of the device attribut

Interface • Status Flag Bit Meaning 0 If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value ex

5.3 Host Commands Table 5.10 Off-line data collection status Status Byte Meaning 00h or 80h Off-line data acquisition is not executed. 02h or 82h

Interface • Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off-line data co

5.3 Host Commands • Error logging capability Table 5.14 Error logging capability Bit Meaning 0 If this bit is 1, it indicates that the drive erro

Interface • SMART error logging If the device detects an unrecoverable error during execution of a command received from the host, the device regis

5.3 Host Commands Table 5.16 Data format of SMART Summary Error Log Byte Item 00 Version of this function 01 Pointer for the latest "Error Lo

Contents CHAPTER 1 Device Overview ... 1-1 1.1 Features ...

Interface • Command data structure Indicates the command received when an error occurs. • Error data structure Indicates the status register when

5.3 Host Commands • SMART self-test The host computer can issue the SMART Execute Off-line Immediate sub-command (FR Register = D4h) and cause the d

Interface Table 5.19 Selective self-test log data structure Offset Description Initial 00h, 01h Data Structure Revision Number 01h, 00h 02h...09h S

5.3 Host Commands • Feature Flags Table 5.20 Selective self-test feature flags Bit Description 0 Vendor specific (unused) 1 When set to one, perf

Interface (17) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value pla

5.3 Host Commands • DEVICE CONFIGURATION RESTORE (FR = C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVI

Interface If the restriction of Multiword DMA modes or Ultra DMA modes is executed, a SET FEATURES command should be issued for the modes restrictio

5.3 Host Commands Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure (1 of 2) Word Value Content 0 X'0002' Data structure revision

Interface Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure (2 of 2) Word Value Content 8-254 X'0000' Reserved 255 X'xxA5&ap

5.3 Host Commands (18) READ MULTIPLE (X’C4’) The READ MULTIPLE Command performs the same as the READ SECTOR(S) Command except that when the device

Contents CHAPTER 3 Installation Conditions...3-1 3.1 Dimensions ...

Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 0 0 0 1 0 0 1F6H(DH) x L x DV Start head No. / LBA [MSB] 1F5H(CH) 1

5.3 Host Commands (19) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (asse

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5

5.3 Host Commands (20) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The blo

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2

5.3 Host Commands (21) READ DMA (X’C8’ or X’C9’) This command operates similarly to the READ SECTOR(S) command except for following events. • The

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5

5.3 Host Commands (22) WRITE DMA (X’CA’ or X’CB’) This command operates similarly to the WRITE SECTOR(S) command except for following events. • Th

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / LBA [MSB] 1F5

5.3 Host Commands (23) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command.

Contents 4.6.2 Write circuit... 4-9 4.6.3 Read circuit..

Interface (24) FLUSH CACHE (X’E7’) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is

5.3 Host Commands (25) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern

Interface (26) IDENTIFY DEVICE (X’EC’) The host system issues the IDENTIFY DEVICE command to read parameter information from the device. Upon rec

5.3 Host Commands (27) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions i

Interface Table 5.22 Information to be read by IDENTIFY DEVICE command (1 of 2) Word Value Description 0 X’045A’ General Configuration *1 1 X’3F

5.3 Host Commands Table 5.22 Information to be read by IDENTIFY DEVICE command (2 of 2) Word Value Description 65 X’0078’ Minimum multiword DMA t

Interface Bit 14-8: Undefined Bit 7: Removable disk drive = 1 Bit 6: Fixed drive = 1 Bit 5-3: Undefined Bit 2: IDENTIFY DEVICE Valid = 0 Bi

5.3 Host Commands *5 Word 50: Device capability Bit 15: 0 Bit 14: 1 Bit 13 to 1 Reserved Bit 0 Standby timer value '1' = Standby time

Interface *10 Word 64: Advance PIO transfer mode support status Bit 15-8: Reserved Bit 7-0: Advance PIO transfer mode Bit 1: 1 = Mode 4 (Bit 0 =

5.3 Host Commands *13 WORD 83 Bit 10:* '1' = 48 bit LBA feature set. Bit 15: = 0 Bit 14: = 1 Bit 13: * '1' = FLUSH CACHE EXT

Contents (13) IDLE (X’97’ or X’E3’)... 5-37 (14) CHECK POWER MODE (X’98’ or X’E5’)..

Interface Bit 5: * '1' = Supports the General Purpose Logging feature set Bit 4: '1' = Supports the Streaming feature set Bit

5.3 Host Commands *16 WORD 86 Bit 15-14: Reserved Bit 13: * '1' = FLUSH CACHE EXT command supported. Bit 12: '1' = FLUSH CACHE

Interface Bit 4: '1' = Valid Configure Stream command has been executed Bit 3-2: Reserved Bit 1: '1' = Supports the SMART SEL

5.3 Host Commands Bits 12-8: In the case of Device 1 (slave drive), a valid value is set. Bit 12: Reserved Bit 11: '1' = Device asserts

Interface *23 WORD 128 Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-6: Reserved Bit 5: '1' = Enhanced securi

5.3 Host Commands (28) SET FEATURES (X’EF’) The host system issues the SET FEATURES command to set parameters in the Features register for the purp

Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 0 1 1 1 1 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F

5.3 Host Commands Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) APM Level 00100 010 (X’22’: Mode 2) Ul

Interface *3) Automatic Acoustic Management (AAM) The host writes to the Sector Count register with the requested acoustic management level and

5.3 Host Commands (29) SECURITY SET PASSWORD (X’F1’) This command enables a user password or master password to be set. The host transfers the 512-

Contents (47) WRITE LOG EXT (X’3F’) [Optional command (Customize)] ...

Interface At command issuance (I-O register contents) 1F7h(CM) 1 1 1 1 0 0 0 1 1F6h(DH) x x x DV xx 1F5h(CH) 1F4h(CL) 1F3h(SN) 1F2h(SC) 1F1h(FR) xx

5.3 Host Commands (30) SECURITY UNLOCK(X’F2’) This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.26 to the dev

Interface At command completion (I-O register contents) 1F7h(ST) Status information 1F6h(DH) x x x DV xx h(CH) 1F4h(CL) h(SN) 1F2h(SC) xx xx xx xx

5.3 Host Commands (31) SECURITY ERASE PREPARE (X’F3’) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE comm

Interface (32) SECURITY ERASE UNIT (X’F4’) This command erases all user data. This command also invalidates the user password and releases the lo

5.3 Host Commands (33) SECURITY FREEZE LOCK (X’F5’) This command puts the device into FROZEN MODE. The following commands used to change the lock

Interface At command issuance (I-O register contents) 1F7h(CM) 1 1 1 1 0 1 0 1 1F6h(DH) x x x DV xx 1F5h(CH) 1F4h(CL) 1F3h(SN) 1F2h(SC) 1F1h(FR)

5.3 Host Commands (34) SECURITY DISABLE PASSWORD (X’F6’) This command invalidates the user password already set and releases the lock function. The

Interface At command completion (I-O register contents) 1F7h(ST) Status information 1F6h(DH) x x x DV xx 1F5h(CH) 1F4h(CL) 1F3h(SN) 1F2h(SC) 1F1h(ER

5.3 Host Commands (35) READ NATIVE MAX ADDRESS (X’F8’) This command posts the maximum address intrinsic to the device, which can be set by the SET

Contents 6.2.1 Power save mode ...6-7 6.2.2 Power commands...

Interface (36) SET MAX (X’F9’) SET MAX features register values Value Command 00h Obsolete 01h SET MAX SET PASSWORD 02h SET MAX LOCK 03h SET M

5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1 0 0 1 1F6H(DH) x L x DV Max head/LBA [MSB] 1F5H(CH)

Interface At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) xx xx

5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1 0 0 1 H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) xx xx x

Interface At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1 0 0 1 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) xx xx xx 1F

5.3 Host Commands At command issuance (I/O registers setting contents) 1F7H(CM) 1 1 1 1 1 0 0 1 1F6H(DH) x x x DV xx 1F5H(CH) 1F4H(CL) 1F3H(SN) xx x

Interface (37) READ SECTOR(S) EXT (X’24’): Option (customizing) • Description This command is the extended command of the READ SECTOR(S) command

5.3 Host Commands (38) READ DMA EXT (X’25’): Option (customizing) • Description This command is the extended command of the READ DMA command. Th

Interface (39) READ NATIVE MAX ADDRESS EXT (X’27’): Option (customizing) • Description This command is used to assign the highest address that t

5.3 Host Commands (40) READ MULTIPLE EXT (X’29’): Option (customizing) • Description This command is the extended command of the READ MULTIPLE co

Contents Illustrations Figures Figure 1.1 Permissible range of +5V rise slope ...1-7 Figure 1.2

Interface (41) READ LOG EXT (X'2F') [Optional command (Customize)] • Description This command reads data from the general-purpose log of

5.3 Host Commands Log address: Log number of the log to be read Sector offset: First log sector subject to the data transfer Sector count: Number

Interface (42) WRITE SECTOR(S) EXT (X’34’): Option (customizing) • Description This command is the extended command of the WRITE SECTOR (S) comm

5.3 Host Commands (43) WRITE DMA EXT (X’35’): Option (customizing) • Description This command is the extended command of the WRITE DMA command.

Interface (44) SET MAX ADDRESS EXT (X’37’): Option (customizing) • Description This command limits specifications so that the highest address th

5.3 Host Commands At command issuance (I/O registers setting contents) 1F7h(CM) 0 0 1 1 0 1 1 1 1F6h(DH) 1 L 1 DV xx 1F5h(CH) P 1F5h(CH) C 1F4h(CL)

Interface (45) WRITE MULTIPLE EXT (X’39’): Option (customizing) • Description This command is the extended command of the WRITE MULTIPLE command

5.3 Host Commands (46) WRITE DMA FUA EXT (X’3D’): Option (customizing) • Description The WRITE DMA FUA EXT command has the difference that report

Interface (47) WRITE LOG EXT (X’3F’) [Optional command (Customize)] • Description This command writes data to the general-purpose log of a device

5.3 Host Commands Log address: Log number of the log to be written Sector offset: First log sector subject to the data transfer Sector count: Numb

FOR SAFE OPERATION Handling of This Manual This manual contains important information for using this product. Read thoroughly before using the produc

Contents Figure 5.1 Interface signals ...5-2 Figure 5.2 Execution

Interface (48) READ VERIFY SECTOR(S) EXT (X’42): Option (customizing) • Description This command is the extended command of the READ VERIFY SECT

5.3 Host Commands (49) WRITE MULTIPLE FUA EXT (X’CE’): Option (customizing) • Description The WRITE MULTIPLE FUA EXT command has the difference t

Interface (50) FLUSH CACHE EXT (X’EA’): Option (customizing) • Description This command executes the same operation as the Flush Cache command (

5.3 Host Commands 5.3.3 Error posting Table 5.27 lists the defined errors that are valid for each command. Table 5.27 Command code and parameters (

Interface Table 5.27 Command code and parameters (2 of 2) Error Register (X '1F1') Status Register (X '1F7') COMMAND NAME ICR

5.4 Command Protocol 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a comman

Interface f) The drive clears DRQ bit to 0. If transfer of another sector is requested, the device sets the BSY bit and steps d) and after are rep

5.4 Command Protocol For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. T

Interface 5.4.2 PIO Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to

5.4 Command Protocol 40 ms Figure 5.5 WRITE SECTOR(S) command protocol For transfer of a sector of data, the host needs to read Status register (X’

Contents Tables Table 1.1 Specifications...1-5 Table 1.2 Exa

Interface 5.4.3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device.

5.4 Command Protocol Figure 5.6 Protocol for the command execution without data transfer 5.4.4 Other commands • READ MULTIPLE (EXT) • WRITE MUL

Interface f) When the command execution is completed, the device clears both BSY and DRQ bits and asserts the INTRQ signal. Then, the host reads t

5.5 Ultra DMA Feature Set 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA comma

Interface Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends the its CRC da

5.5 Ultra DMA Feature Set 8) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-. Once the device has driven DSTROBE the devic

Interface STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and w

5.5 Ultra DMA Feature Set assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is t

Interface 4) If the host negates HDMARDY- within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero

5.5 Ultra DMA Feature Set 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the o

Contents xviii C141-E258 Table 5.28 Recommended series termination for Ultra DMA ...5-148 Table 5.29 Ultra DMA data burst

Interface 5.5.4.2 The data out transfer The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6

5.5 Ultra DMA Feature Set 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall

Interface b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifica

5.5 Ultra DMA Feature Set 13) The host shall neither negate STOP nor HSTROBE until at least tACK after negating DMACK-. 14) The host shall not asse

Interface i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for ca

5.6 Timing 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. t6t12t11t10t5t4

Interface 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. CS0-/CS1-t

5.6 Timing 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.23 con

Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.29 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 (in ns) MODE

5.6 Timing Table 5.29 Ultra DMA data burst timing requirements (2 of 2) MODE 0 (in ns) MODE 1 (in ns) MODE 2(in ns) MODE 3(in ns) MODE 4(in ns) MODE

CHAPTER 1 Device Overview 1.1 Features 1.2 Device Specifications 1.3 Power Requirements 1.4 Environmental Specifications 1.5 Acoustic Noise 1.6 Shoc

Interface Table 5.30 Ultra DMA sender and recipient timing requirements MODE 0 (in ns) MODE 1 (in ns) MODE 2(in ns) MODE 3(in ns) MODE 4(in ns) M

5.6 Timing 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DSTROBE

Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. tRPtRFS DMAR

5.6 Timing 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ

Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (d

5.6 Timing 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (devic

Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. at host

5.6 Timing 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (de

Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

5.6 Timing 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the disk drive are described. (1) Compact The disk drive ha

Interface 5-164 C141-E258 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master dev

CHAPTER 6 Operations 6.1 Device Response to the Reset 6.2 Power Save 6.3 Defect Processing 6.4 Read-ahead Cache 6.5 Write Cache C141-E258 6-1

Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on

6.1 Device Response to the Reset Max. 31 sec.Max. 450 ms.Max. 30 sec.Max. 1 ms.If presence of a slave device isconfirmed, PDIAG- is checked forup to

Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to

6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slav

Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is presen

6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power s

Operations • Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The

6.3 Defect Processing 6.2.2 Power commands The following commands are available as power commands. • IDLE • IDLE IMMEDIATE • STANDBY • STANDBY I

1.1 Features (3) Low noise and vibration In Ready status (while the device is waiting for any commands), the Sound Power level of the disk drive i

Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Secto

6.3 Defect Processing (3) Automatic alternating processing This technology assigns a defective sector to a spare sector of a spare cylinder for alte

Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order

6.4 Read-ahead Cache 6.4.2 Caching operation The caching operation is performed only when the commands listed below are received. If any of the fol

Operations 1)-1 Any command other than the following commands is issued. (All caching-target data is invalidated.) RECALIBRATE IDLE IMMEDIATE DOWNLO

6.4 Read-ahead Cache 6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for following situations. 6.4.3.1 M

Operations 6.4.3.2 Sequential hit When the read command that is targeted at a sequential address is received after execution of the read commands i

6.4 Read-ahead Cache 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data

Operations 6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from wr

6.5 Write Cache <Exception> • If a Reset or command is received while a transfer of one sector of data is in progress, data is not written in

Device Overview (8) Drive-specific function (specification) The disk drive measures the environment temperature. When the temperature becomes abo

Operations 6-20 C141-E258 If Write Cache is enabled, there is a possibility that data transferred from the host with the Write Cache enable comman

Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT

Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failur

Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicat

This page is intentionally left blank.

Acronyms and Abbreviations A ABRT Aborted command AIC Automatic idle control AMNF Address mark not found ATA AT attachment AWG American wire gag

This page is intentionally left blank.

Index caching function when power supply is turned on... 6-19 1 drive connection...

Index error rate ...1-13 DATA buffer structure ... 6-12 error register...

Index mean time to repair (MTTR) ... 1-12 host command ... 5-14 media defect ...

1.2 Device Specifications Table 1.1 Specifications (1 of 2) MHW2060AC MHW2040AC Format Capacity (*1) 60 GB 40 GB Number of Sectors (User) 117

Index sector number register...5-10 power supply connector (CN1) ... 3-10 sector slip processing...

Index specification summary ... 1-4 spindle ... 4-2 spindle motor...

This page is intentionally left blank.

Comment Form We would appreciate your comments and suggestions regarding this manual. Manual code C141-E258-03EN Manual name MHW2060AC, MHW2040AC

This page is intentionally left blank.

MHW2060AC, MHW2040AC DISK DRIVES PRODUCT MANUAL C141-E258-03EN MHW2060AC, MHW2040AC DISK DRIVES PRODUCT MANUAL C141-E258-03EN

Device Overview Table 1.1 Specifications (2 of 2) Model Capacity (*) No. of Cylinder No. of Heads No. of Sectors MHW2060AC 8.45 GB 16,383 16

1.3 Power Requirements 1.3 Power Requirements (1) Input Voltage • + 5 V ± 5 % (2) Ripple +5 V Maximum 100 mV (peak to peak) Frequency DC

Revision History (1/1) Edition Date Revised section (*1) (Added/Deleted/Altered) Details 01 2007-02-28 — — 02 2007-06-15 Entire manual (added) Ad

Device Overview (4) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned off and, a thing with no ringing. Pe

1.3 Power Requirements (5) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Curr

Device Overview (6) Current fluctuation (Typ.) at +5 V when power is turned on Figure 1.3 Current fluctuation (Typ.) at +5 V when power is turned

1.5 Acoustic Noise 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification

Device Overview 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 8760 H/year or less Operating tim

1.8 Error Rate abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment). 1.8 Error Rate

Device Overview Emergency Unload other than Unload is performed when the power is shut down while the heads are still loaded on the disk. The produc

1.11 Advanced Power Management (APM) Standby: The spindle motor stops. In APM Mode-1, which is the APM default mode, the operation status shifts

This page is intentionally left blank.

CHAPTER 2 Device Configuration 2.1 Device Configuration 2.2 System Configuration This chapter describes the internal configurations of the hard

This page is intentionally left blank.

Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamp

2.2 System Configuration (6) Read/write circuit The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliabilit

Device Configuration 2-4 C141-E258 2.2.3 2 drives connection (Host adaptor) MHW2060AC MHW2040AC MHW2060AC MHW2040AC Note: When the drive th

CHAPTER 3 Installation Conditions 3.1 Dimensions 3.2 Mounting 3.3 Cable Connections 3.4 Jumper Settings This chapter gives the external dimensio

Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dime

3.2 Mounting 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)." (1) Orientation Th

Installation Conditions Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown

3.2 Mounting (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 c

Installation Conditions (5) Service area Figure 3.5 shows how the drive must be accessed (service areas) during and after installation. Mounting scr

3.2 Mounting - General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation t

Preface This manual describes MHW2060AC, and MHW2040AC models of the MHW Series, 2.5-inch hard disk drives. This drive has a built-in controller that

Installation Conditions 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting e

3.3 Cable Connections 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable

Installation Conditions 3.3.4 Power supply connector (CN1) Figure 3.9 shows the pin assignment of the power supply connector (CN1). Figure 3.9 P

3.4 Jumper Settings 3.4.2 Factory default setting Figure 3.11 shows the default setting position at the factory. Open Figure 3.11 Factory default

Installation Conditions 3.4.4 CSEL setting Figure 3.13 shows the cable select (CSEL) setting. ShortOpenBD2AC1 Note: The CSEL setting is not depen

3.4 Jumper Settings drive drive Figure 3.15 Example (2) of cable select 3.4.5 Power up in standby setting When pin C is grounded, the drive does

This page is intentionally left blank.

CHAPTER 4 Theory of Device Operation 4.1 Outline 4.2 Subassemblies 4.3 Circuit Configuration 4.4 Power-on Sequence 4.5 Self-calibration 4.6 Read/writ

Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk dri

4.3 Circuit Configuration 4.2.4 Air filter There are two types of air filters: a breather filter and a circulation filter. The breather filter make

Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert

Theory of Device Operation (4) Controller circuit Major functions are listed below. • ATA interface control and data transfer control • Data buffe

4.3 Circuit Configuration MCU & HDC & RDC HDC MCURDC Data Buffer SDRAM SVC ResonatorR/W Pre-Amp ThermistorVCMHEAD SP Motor Media DE PCA AT

Theory of Device Operation 4.4 Power-on Sequence Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is describ

4.5 Self-calibration 4.5 Self-calibration The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external

Theory of Device Operation 4.5.2 Execution timing of self-calibration Self-calibration is performed once when power is turned on. After that, the

4.6 Read/write Circuit 4.6 Read/write Circuit The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read c

Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then

4.6 Read/write Circuit (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Mo

Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is contro

4.7 Servo Control (1) Microprocessor unit (MPU) The MPU executes startup of the spindle motor, movement to the reference cylinder, seek to the spec

Preface Representation of the data storage capacity in this manual One gigabyte (GB) = one billion bytes; accessible capacity will be less and actu

Theory of Device Operation (6) Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control c

4.7 Servo Control 4.7.2 Data-surface servo format Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to

Theory of Device Operation Circumference Direction Erase: DC erase area OGB Data area IGB expand Servo frame (172 servo frames per revoluti

4.7 Servo Control 4.7.3 Servo frame format As the servo information, the IDD uses the phase signal servo generated from the gray code and servo EVEN

Theory of Device Operation 4.7.4 Actuator motor control The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the dat

4.7 Servo Control 4.7.5 Spindle motor control Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3-phase full/half-wave

This page is intentionally left blank.

CHAPTER 5 Interface 5.1 Physical Interface 5.2 Logical Interface 5.3 Host Commands 5.4 Command Protocol 5.5 Ultra DMA Feature Set 5.6 Timing Th

Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Figure 5

5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal

This page is intentionally left blank.

Interface [Signal] [I/O] [Description] ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Set

5.1 Physical Interface [Signal] [I/O] [Description] CS0- I Chip select signal decoded from the host address bus. This signal is used by the host

Interface [Signal] [I/O] [Description] DMARQ O This signal is used for DMA transfer between the host system and the device. The device asserts

5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input-output (I/O) registers of the d

Interface Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectivel

5.2 Logical Interface - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bi

Interface (5) Sector Number register (X’1F3’) The contents of this register indicate the starting sector number for the subsequent command. The s

5.2 Logical Interface (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITI

Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is comple

5.2 Logical Interface (10) Command register (X’1F7’) The Command register contains a command code being sent to the device. After this register is

Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in

Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 Bit 5 Bit

5.3 Host Commands Table 5.3 Command code and parameters (1 of 2) COMMAND CODE (Bit) PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DHRECAL

Interface Table 5.3 Command code and parameters (2 of 2) COMMAND CODE (Bit) PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DHFLUSH CACHE

5.3 Host Commands Note: READ LONG (0x22) command/WRITE LONG (0x33) command became a unsupport from the MHW2xxxAT series. Notes: FR: Features Registe

Interface 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O

5.3 Host Commands SC: Sector Count register x, xx: Do not care (no necessary to set) Note: 1. When the L bit is specified to 1, the lower 4 bits

Interface (1) RECALIBRATE (X’10’ to X’1F’) This command performs the calibration. Upon receipt of this command, the device sets BSY bit of the St

5.3 Host Commands (2) READ SECTOR(S) (X’20’ or X’21’) This command reads data of sectors specified in the Sector Count register from the address sp

Interface (R: Retry) At command completion (I/O registers contents to be read) 1F7H(ST) Status information 1F6H(DH) x L x DV End head No. / L

5.3 Host Commands (3) WRITE SECTOR(S) (X’30’ or X’31’) This command writes data of sectors from the address specified in the Device/Head, Cylinder