Fujitsu MHE2064AT User Manual

C141-E057-02ENMHE2064AT, MHE2043ATMHF2043AT, MHF2021ATDISK DRIVEPRODUCT MANUAL

C141-E057-02EN vImportant Alert ItemsImportant Alert MessagesThe important alert messages in this manual are as follows:A hazardous situation could re

5.3 Host CommandsC141-E057-01EN 5-25(6) WRITE MULTIPLE (X’C5’)This command is similar to the WRITE SECTOR(S) command. The device doesnot generate int

Interface5-26 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 0 0 0 1 0 11F6H(DH)×L×DVStart head No. /LBA [MSB]1F5H(CH)1

5.3 Host CommandsC141-E057-01EN 5-27A host system can select the following transfer mode using the SET FEATUREScommand.1) Single word DMA transfer mo

Interface5-28 C141-E057-01ENAfter all sectors are verified, the last interruption (INTRQ for commandtermination) is generated.At command issuance (I/O

5.3 Host CommandsC141-E057-01EN 5-29At command issuance (I/O registers setting contents)1F7H(CM)0 0 0 1xxxx1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1

Interface5-30 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)0 1 1 1xxxx1F6H(DH)×L×DVHead No. /LBA [MSB]1F5H(CH)1F4H(CL)1F3

5.3 Host CommandsC141-E057-01EN 5-31At command issuance (I/O registers setting contents)1F7H(CM)1 0 0 1 0 0 0 11F6H(DH)× × ×DVMax. head No.1F5H(CH)1F

Interface5-32 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 1 0 1 1 0 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(S

5.3 Host CommandsC141-E057-01EN 5-33Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 7)Word ValueDescription23-26–Firmware revision

Interface5-34 C141-E057-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (3 of 7)WordValueDescription83X’4008’Support of command sets

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5.3 Host CommandsC141-E057-01EN 5-35Table 5.4 Information to be read by IDENTIFY DEVICE command (5 of 7)Bit 9, 8: Always 1*4 Word 51: PIO data trans

Interface5-36 C141-E057-01ENTable 5.4 Information to be read by IDENTIFY DEVICE command (6 of 7)Bit 2: ATA-2 supported = 1Bit 1: ATA-1 supported = 1Bi

5.3 Host CommandsC141-E057-01EN 5-37Table 5.4 Information to be read by IDENTIFY DEVICE command (7 of 7)*12 WORD 85Bits 15-9 : Same definition as WOR

Interface5-38 C141-E057-01EN(13) IDENTIFY DEVICE DMA (X’EE’)When this command is not used to transfer data to the host in DMA mode, thiscommand funct

5.3 Host CommandsC141-E057-01EN 5-39Table 5.5 Features register values and settable modesFeatures RegisterDrive operation modeX’02’Enables the write

Interface5-40 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 1 0 1 1 1 11F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(S

5.3 Host CommandsC141-E057-02EN 5-41Single word DMA transfer mode X 00010 000 (X’10’: Mode 0)00010 001 (X’11’: Mode 1)00010 010 (X’12’: Mode 2)

Interface5-42 C141-E057-01ENWhen the SET MULTIPLE MODE command operation is completed, the deviceclears the BSY bit and generates an interrupt.At comm

5.3 Host CommandsC141-E057-01EN 5-43Word 47Bit 7-0 = 10:Word 59 = 0000:= 00xx:Maximum number of sectors that can be transferred per interruptby the R

Interface5-44 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 1 1 1 0 0 11F6H(DH)×L×DVMax head/LBA [MSB]1F5H(CH)Max. cyl

C141-E057-02EN viiManual OrganizationMHE2064AT, MHE2043ATMHF2043AT, MHF2021ATDISK DRIVEPRODUCT MANUAL(C141-E057)<This manual>• Device Overview•

5.3 Host CommandsC141-E057-01EN 5-45At command completion (I/O registers contents to be read)1F7H(ST)Status information1F6H(DH)× × ×DVMax head/LBA [M

Interface5-46 C141-E057-01ENTable 5.6 Diagnostic codeCodeResult of diagnosticX’01’X’03’X’05’X’8x’No error detected.Data buffer compare errorROM sum ch

5.3 Host CommandsC141-E057-01EN 5-47(19) READ LONG (X’22’ or X’23’)This command operates similarly to the READ SECTOR(S) command except thatthe devi

Interface5-48 C141-E057-01EN(20) WRITE LONG (X’32’ or X’33’)This command operates similarly to the READ SECTOR(S) command except thatthe device writ

5.3 Host CommandsC141-E057-01EN 5-49(21) READ BUFFER (X’E4’)The host system can read the current contents of the sector buffer of the device byissui

Interface5-50 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)1 1 1 1 1 0 0 01F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(S

5.3 Host CommandsC141-E057-01EN 5-51Sector Count register valuePoint of timer0[X’00’]30 minutes1 to 3 [X’01’ to X’03’]15 seconds4 to 240 [X’04’ to X’

Interface5-52 C141-E057-01EN(24) IDLE IMMEDIATE (X’95’ or X’E1’)Upon receipt of this command, the device sets the BSY bit of the Status register,and

5.3 Host CommandsC141-E057-01EN 5-53Under the standby mode, the spindle motor is stopped. Thus, when the commandinvolving a seek such as the READ SE

Interface5-54 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)X’94’ or X’E0’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC

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5.3 Host CommandsC141-E057-01EN 5-55At command issuance (I/O registers setting contents)1F7H(CM)X’99’ or X’E6’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(S

Interface5-56 C141-E057-01ENAt command issuance (I/O registers setting contents)1F7H(CM)X’98’ or X’E5’1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC

5.3 Host CommandsC141-E057-01EN 5-57Table 5.7 Features Register values (subcommands) and functionsFeatures ResisterFunctionX’D0’SMART Read Attribute

Interface5-58 C141-E057-01ENFeatures ResisterFunctionX’DA’SMART Return Status:When the device receives this subcommand, it asserts the BSY bitand save

5.3 Host CommandsC141-E057-01EN 5-59At command completion (I-O registers setting contents)1F7H(ST)Status information1F6H(DH)× × ×DVxx1F5H(CH)1F4H(CL)

Interface5-60 C141-E057-01ENTable 5.9 Format of insurance failure threshold value dataByteItem0001Data format version number02Attribute 1Attribute ID0

5.3 Host CommandsC141-E057-01EN 5-61Attribute IDAttribute name12Number of power-on-power-off times13 to 198(Reserved)199Ultra ATA CRC error rate200Wr

Interface5-62 C141-E057-01ENBit 7: If this bit is 1, it indicates that the automatic off-line datacollection function is enabled.Status ByteMeaning0Of

5.3 Host CommandsC141-E057-01EN 5-63• Check sumTwo’s complement of the lower byte, obtained by adding 511-byte data onebyte at a time from the beginn

Interface5-64 C141-E057-01ENTable 5.10 Contents of security passwordWordContents0Control wordBit 0: Identifier0 = Compares the user passwords.1 = Com

C141-E057-01EN ixContentsCHAPTER 1 Device Overview... 1-11.1 Features 1-21.1.

5.3 Host CommandsC141-E057-01EN 5-65At command issuance (I-O register contents)1F7h(CM)1 1 1 1 0 0 1 11F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(S

Interface5-66 C141-E057-01ENAt command issuance (I-O register contents)1F7h(CM)1 1 1 1 0 1 0 01F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F1h(FR

5.3 Host CommandsC141-E057-01EN 5-67• READ DMA• WRITE DMA• SECURITY DISABLE PASSWORD• READ LONG• WRITE LONG• SECURITY FREEZE LOCK• READ MULTIPLE• WRI

Interface5-68 C141-E057-01EN(34) SECURITY SET PASSWORD (F1h)This command enables a user password or master password to be set.The host transfers the

5.3 Host CommandsC141-E057-01EN 5-69Table 5.12 Relationship between combination of Identifier and Security level, andoperation of the lock functionIn

Interface5-70 C141-E057-01ENIssuing this command in FROZEN MODE returns the Aborted Command error.At command issuance (I-O register contents)1F7h(CM)1

5.3 Host CommandsC141-E057-01EN 5-71At command issuance (I-O register contents)1F7h(CM)111001111F6h(DH)× × ×DVxx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F1h(

Interface5-72 C141-E057-01ENTable 5.13 Command code and parameters (2 of 2)Command nameError register (X’1F1’)Status register (X’1F7’)BBKUNCINDFABRTTK

5.4 Command ProtocolC141-E057-01EN 5-735.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0prior to

Interface5-74 C141-E057-01ENwords, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the DRQ status by

Contentsx C141-E057-01ENCHAPTER 3 Installation Conditions...3-13.1 Dimensions 3-23.2 Mo

5.4 Command ProtocolC141-E057-01EN 5-75sector in multiple-sector reading. If the timing to read the Status register does not meetabove condition, no

Interface5-76 C141-E057-01ENb) The host writes a command code in the Command register. The drive sets theBSY bit of the Status register.c) When the de

5.4 Command ProtocolC141-E057-01EN 5-77Note:For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order toclear INTRQ

Interface5-78 C141-E057-01ENFigure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands• READ MULTIPLE• SLEEP• WRITE MULTI

5.4 Command ProtocolC141-E057-01EN 5-79f) When the command execution is completed, the device clears both BSY andDRQ bits and asserts the INTRQ signa

Interface5-80 C141-E057-01EN5.5 Ultra DMA Feature Set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and WRITEDMA commands.

5.5 Ultra DMA Feature SetC141-E057-01EN 5-81Both the host and device perform a CRC function during an Ultra DMA burst. Atthe end of an Ultra DMA burs

Interface5-82 C141-E057-01ENg) Ultra DMA data in burstThe device should not invert the state of this signal in the period from themoment of STOP signa

5.5 Ultra DMA Feature SetC141-E057-01EN 5-83f) Once the transmitting side has outputted the ending request, the output stateof STROBE signal should no

Interface5-84 C141-E057-01EN9) The host shall negate STOP and assert HDMARDY- within tENV afterasserting DMACK-. After negating STOP and asserting HD

ContentsC141-E057-01EN xi4.6.1 Read/write preamplifier (PreAMP) 4-94.6.2 Write circuit 4-104.6.3 Read circuit 4-124.6.4 Digital PLL circui

5.5 Ultra DMA Feature SetC141-E057-01EN 5-853) The device shall resume an Ultra DMA burst by generating a DSTROBEedge.b) Host pausing an Ultra DMA dat

Interface5-86 C141-E057-01EN7) If DSTROBE is negated, the device shall assert DSTROBE within tLIafter the host has asserted STOP. No data shall be tr

5.5 Ultra DMA Feature SetC141-E057-01EN 5-875) The host shall assert STOP no sooner than tRP after negatingHDMARDY-. The host shall not negate STOP a

Interface5-88 C141-E057-01EN5.5.4 Ultra DMA data out commands5.5.4.1 Initiating an Ultra DMA data out burstThe following steps shall occur in the orde

5.5 Ultra DMA Feature SetC141-E057-01EN 5-89HSTROBE edge no more frequently than tCYC for the selected Ultra DMAMode. The host shall not generate two

Interface5-90 C141-E057-01EN5.5.4.4 Terminating an Ultra DMA data out bursta) Host terminating an Ultra DMA data out burstThe following stops shall oc

5.5 Ultra DMA Feature SetC141-E057-01EN 5-91b) Device terminating an Ultra DMA data out burstThe following steps shall occur in the order they are lis

Interface5-92 C141-E057-01EN13) The host shall neither negate STOP nor HSTROBE until at least tACK afternegating DMACK-.14) The host shall not assert

5.5 Ultra DMA Feature SetC141-E057-01EN 5-93Note: Since no bit clock is available, the recommended approach forcalculating CRC is to use a word clock

Interface5-94 C141-E057-01EN5.5.6 Series termination required for Ultra DMASeries termination resistors are required at both the host and the device f

Contentsxii C141-E057-01EN5.5.2 Phases of operation 5-815.5.2.1 Ultra DMA burst initiation phase 5-815.5.2.2 Data transfer phase 5-825.5.2

5.6 TimingC141-E057-01EN 5-955.6 Timing5.6.1 PIO data transferFigure 5.10 shows of the data transfer timing between the device and the hostsystem.

Interface5-96 C141-E057-01ENFigure 5.10 Data transfer timing

5.6 TimingC141-E057-01EN 5-975.6.2 Single word DMA data transferFigure 5.9 show the single word DMA data transfer timing between the deviceand the ho

Interface5-98 C141-E057-01EN5.6.3 Multiword DMA data transferFigure 5.10 shows the multiword DMA data transfer timing between the deviceand the host s

5.6 TimingC141-E057-01EN 5-995.6.4 Transfer of Ultra DMA dataFigures 5.13 to 5.22 define the timings concerning every phase for the Ultra DMABurst.Ta

Interface5-100 C141-E057-01EN5.6.4.2 Ultra DMA data burst timing requirementsTable 5.16 Ultra DMA data burst timing requirements (1 of 2)NAMEMODE 0(in

5.6 TimingC141-E057-01EN 5-101Table 5.16 Ultra DMA data burst timing requirements (2 of 2)NAMEMODE 0(in ns)MODE 1(in ns)MODE 2(in ns)COMMENTMIN MAX M

Interface5-102 C141-E057-01EN5.6.4.3 Sustained Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.Note

5.6 TimingC141-E057-01EN 5-1035.6.4.4 Host pausing an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Mo

Interface5-104 C141-E057-01EN5.6.4.5 Device terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DM

ContentsC141-E057-01EN xiiiCHAPTER 6 Operations... 6-16.1 Device Respons

5.6 TimingC141-E057-01EN 5-1055.6.4.6 Host terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra DM

Interface5-106 C141-E057-01EN5.6.4.7 Initiating an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes

5.6 TimingC141-E057-01EN 5-1075.6.4.8 Sustained Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA Modes.N

Interface5-108 C141-E057-01EN5.6.4.9 Device pausing an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra DMA M

5.6 TimingC141-E057-01EN 5-1095.6.4.10 Host terminating an Ultra DMA data out burst5.6.4.2 contains the values for the timings for each of the Ultra

Interface5-110 C141-E057-01EN5.6.4.11 Device terminating an Ultra DMA data in burst5.6.4.2 contains the values for the timings for each of the Ultra D

5.6 TimingC141-E057-01EN 5-1115.6.5 Power-on and resetFigure 5.11 shows power-on and reset (hardware and software reset) timing.(1) Only master devic

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C141-E057-01EN 6-1CHAPTER 6 Operations6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cache6.

Operations6-2 C141-E057-01EN6.1 Device Response to the ResetThis section describes how the PDIAG- and DASP- signals responds when thepower of the IDD

Contentsxiv C141-E057-01ENIllustrationsFiguresFigure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7Figure 2.1 Disk drive outerv

6.1 Device Response to the ResetC141-E057-01EN 6-3Figure 6.1 Response to power-on31 sec.30 sec.

Operations6-4 C141-E057-01EN6.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to thepower-on reset.

6.1 Device Response to the ResetC141-E057-01EN 6-56.1.3 Response to software resetThe master device does not check the DASP- signal for a software re

Operations6-6 C141-E057-01EN6.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave devi

6.2 Address TranslationC141-E057-02EN 6-76.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium,the IDD al

Operations6-8 C141-E057-01EN6.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head(PH) 0, and

6.3 Power SaveC141-E057-01EN 6-9(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0,physical head 0, and physical

Operations6-10 C141-E057-01EN• Standby mode• Sleep modeThe drive moves from the Active mode to the idle mode by itself.Regardless of whether the power

6.4 Defect ManagementC141-E057-01EN 6-11When one of following commands is issued, the command is executed normallyand the device is still stayed in t

Operations6-12 C141-E057-01EN6.4.1 Spare areaFollowing two types of spare area are provided for every physical head.1) Spare cylinder for sector slip:

C141-E057-01ENFOR SAFE OPERATIONHandling of This ManualThis manual contains important information for using this product. Read thoroughly before usin

ContentsC141-E057-02EN xvFigure 5.5 WRITE SECTOR(S) command protocol 5-76Figure 5.6 Protocol for the command execution without data transfer 5

6.4 Defect ManagementC141-E057-01EN 6-13(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder

Operations6-14 C141-E057-01EN6.5 Read-Ahead CacheAfter read command which involes read data from the disk medium is completed,the read-ahead cache fun

6.5 Read-Ahead CacheC141-E057-01EN 6-15• READ SECTOR (S)• READ MULTIPLE• READ DMAWhen caching operation is disabled by the SET FEATURES command, nocac

Operations6-16 C141-E057-01EN− READ MULTIPLE− WRITE SECTOR(S)− WRITE MULTIPLE− WRITE VERIFY SECTOR(S)3) Caching operation is inhibited by the SET FEAT

6.5 Read-Ahead CacheC141-E057-01EN 6-172) Transfers the requested data that already read to the host system with readingthe requested data from the di

Operations6-18 C141-E057-01EN1) At receiving the sequential read command, the disk drive sets the DAP andHAP to the start address of the segment and r

6.5 Read-Ahead CacheC141-E057-01EN 6-19b. Sequential hitWhen the previously executed read command is the sequential commandand the last sector address

Operations6-20 C141-E057-01EN4) Finally, the cache data in the buffer is as follows.Read-ahead datac. Non-sequential command immediately after sequent

6.5 Read-Ahead CacheC141-E057-01EN 6-213) The cache data for next read command is as follows.Cache data6.5.3.4 Partially hitA part of requested data i

Operations6-22 C141-E057-01EN3) The cache data for next read command is as follows.Cache data6.6 Write CacheThe write cache function of the drive make

Contentsxvi C141-E057-01ENTable 3.1 Surface temperature measurement points and standard values3-6Table 3.2 Cable connector specifications 3-9Table

6.6 Write CacheC141-E057-01EN 6-23The drive uses a cache data of the last write command as a read cache data. Whena read command is issued to the sa

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C141-E057-01EN GL-1GlossaryActuatorHead positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (

GlossaryGL-2 C141-E057-01ENMTBFMean time between failures. The MTBF is calculated by dividing the totaloperation time (total power-on time) by the nu

GlossaryC141-E057-01EN GL-3StatusThe status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The

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C141-E057-01EN AB-1Acronyms and AbbreviationsAABRT Abored commandAIC Automatic idle controlAMNF Address mark not foundATA AT attachmentAWG American wi

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C141-E057-01EN IN-1Index1-drive connection 2-42-drive connection 2-58/8 GCR 4-108/9 GCR decoder 4-13AAcceleration mode 4-21Acoustic noise

IndexIN-2 C141-E057-01ENData that is object of caching operation6-15Data transfer rate 4-13Data transferring command 5-73, 5-75Data transfer timin

C141-E057-01EN 1-1CHAPTER 1 Device Overview1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic Noi

IndexC141-E057-01EN IN-3MMaster 1-3Master drive setting 3-10Master password 5-68Mean time between failures 1-8Mean time to repair 1-8Media d

IndexIN-4 C141-E057-01ENSEEK 5-29Seek operation 4-20Seek to specified cylinder 4-15Self-calibration 4-7Self-calibration content 4-7Self-diag

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C141-E057-02ENComment FormWe would appreciate your comments and suggestions regarding this manual.Manual codeC141-E057-02ENManual nameMHE2064AT, MHE20

C141-E057-02ENC141-E057-02ENMHE2064/2043AT, MHF2043/2021AT DISK DRIVEPRODUCT MANUALMHE2064/2043AT, MHF2043/2021AT DISK DRIVEPRODUCT MANUAL

Device Overview1-2 C141-E057-02EN1.1 Features1.1.1 Functions and performanceThe fillowing features of the MHE Series and MHF Series are described.(1)

1.1 FeaturesC141-E057-01EN 1-31.1.3 Interface(1) Connection to interfaceWith the built-in ATA interface controller, the disk drives (the MHE Series a

Device Overview1-4 C141-E057-02EN1.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specfications of the disk drives (MHE2064AT/

1.2 Device SpecificationsC141-E057-02EN 1-5Table 1.2 shows the specfications of the disk drives (MHF2043AT/MHF2021AT).Table 1.2 Specifications (MHF20

Device Overview1-6 C141-E057-02ENUnder the CHS mode (normal BIOS specification), formatted capacity,number of cylinders, number of heads, and number o

1.3 Power RequirementsC141-E057-01EN 1-7(3) Current Requirements and Power DissipationTable 1.5 lists the current and power dissipation.Table 1.5 Cur

Device Overview1-8 C141-E057-01EN(5) Power on/off sequenceThe voltage detector circuits (the MHE Series and MHF Series) monitor +5 V.The circuits do n

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1.6 Shock and VibrationC141-E057-02EN 1-91.5 Acoustic NoiseTable 1.7 lists the acoustic noise specification.Table 1.7 Acoustic noise specificationIte

Device Overview1-10 C141-E057-01EN1.7 Reliability(1) Mean time between failures (MTBF)Conditions of 300,000 hCurrent time250H/month or less 3000H/yea

1.9 Media DefectsC141-E057-02EN 1-111.8 Error RateKnown defects, for which alternative blocks can be assigned, are not included inthe error rate coun

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C141-E057-01EN 2-1CHAPTER 2 Device Configuration2.1 Device Configuration2.2 System ConfigurationThis chapter describes the internal configurations of

Device Configuration2-2 C141-E057-02EN2.1 Device ConfigurationFigure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/

2.1 Device ConfigurationC141-E057-02EN 2-3MHE2064AT345Head120MHE2043AT3120MHF2043AT3HeadHead120HeadMHF2021AT10Figure 2.2 Configuration of disk media

Device Configuration2-4 C141-E057-02EN2.2 System Configuration2.2.1 ATA interfaceFigures 2.3 and 2.4 show the ATA interface system configuration. The

2.2 System ConfigurationC141-E057-01EN 2-5HA (host adaptor) consists of address decoder, driver, and receiver.ATA is an abbreviation of “AT attachmen

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C141-E057-02ENRevision History(1/1)Edition Date Revised section (*1)(Added/Deleted/Altered)Details01 1998-06-20 — —02 1998-09-10*1 Section(s) with ast

C141-E057-01EN 3-1CHAPTER 3 Installation Conditions3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper SettingsThis chapter gives the external d

Installation Conditions3-2 C141-E057-01EN3.1 DimensionsFigure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw hole

3.1 DimensionsC141-E057-01EN 3-3Figure 3.1 Dimensions (MHF series) (2/2)

Installation Conditions3-4 C141-E057-01EN3.2 Mounting(1) OrientationFigure 3.2 illustrates the allowable orientations for the disk drive.

3.2 MountingC141-E057-01EN 3-5(2) FrameThe MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG.Use M3 screw fo

Installation Conditions3-6 C141-E057-01EN(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to theambient t

3.2 MountingC141-E057-02EN 3-7(5) Service areaFigure 3.5 shows how the drive must be accessed (service areas) during and afterinstallation.Figure 3.5

Installation Conditions3-8 C141-E057-01EN3.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for c

3.3 Cable ConnectionsC141-E057-01EN 3-93.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors.Ta

Installation Conditions3-10 C141-E057-01EN3.3.4 Power supply connector (CN1)Figure 3.8 shows the pin assignment of the power supply connector (CN1).Fi

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3.4 Jumper SettingsC141-E057-02EN 3-113.4.2 Factory default settingFigure 3.10 shows the default setting position at the factory.Figure 3.10 Factory

Installation Conditions3-12 C141-E057-02EN3.4.4 CSEL settingFigure 3.12 shows the cable select (CSEL) setting.ShortOpenBD2AC1Note:The CSEL setting is

3.4 Jumper SettingsC141-E057-01EN 3-13Figure 3.14 Example (2) of Cable Select

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C141-E057-01EN 4-1CHAPTER 4 Theory of Device Operation4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on Sequence4.5 Self-calibration4.

Theory of Device Operation4-2 C141-E057-02EN4.1 OutlineThis chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of

4.2 SubassembliesC141-E057-02EN 4-3MHE2064AT345Head120MHE2043AT3120MHF2043AT3HeadHead120HeadMHF2021AT10Figure 4.1 Head structure4.2.3 SpindleThe spin

Theory of Device Operation4-4 C141-E057-01EN4.3 Circuit ConfigurationFigure 4.2 shows the disk drive circuit configuration.(1) Read/write circuitThe r

4.3 Circuit ConfigurationC141-E057-01EN 4-5Figure 4.2 Circuit Configuration16 bit

Theory of Device Operation4-6 C141-E057-01EN4.4 Power-on SequenceFigure 4.3 describes the operation sequence of the disk drive at power-on. Theoutlin

C141-E057-01EN iPrefaceThis manual describes the MHE Series and MHF Series, 2.5-inch hard disk drives.These drives have a built-in controller that is

4.5 Self-calibrationC141-E057-01EN 4-7Figure 4.3 Power-on operation sequence4.5 Self-calibrationThe disk drive occasionally performs self-calibration

Theory of Device Operation4-8 C141-E057-01ENThe forces are compensated by adding the measured value to the specified currentvalue to the power amplifi

4.6 Read/write CircuitC141-E057-01EN 4-9Table 4.1 Self-calibration execution timechartTime elapsedTime elapsed(accumulated)1At power-onInitial calibr

Theory of Device Operation4-10 C141-E057-01ENsignal (WUS) when a write error occurs due to head short-circuit or headdisconnection.The Pre AMP sets th

4.6 Read/write CircuitC141-E057-01EN 4-11Figure 4.4 Read/write circuit block diagram

Theory of Device Operation4-12 C141-E057-01EN4.6.3 Read circuitThe head read signal from the PreAMP is regulated by the automatic gain control(AGC) ci

4.6 Read/write CircuitC141-E057-01EN 4-13(3) Flash digitizer circuitThis circuit is 10-tap sampled analog transversal filter circuit that cosine-equa

Theory of Device Operation4-14 C141-E057-01EN4.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. Theactuator mo

4.7 Servo ControlC141-E057-01EN 4-15The major internal operations are listed below.a. Spindle motor startStarts the spindle motor and accelerates it

Theory of Device Operation4-16 C141-E057-01ENFigure 4.7 Physical sector servo configuration on disk surfaceServo frame(60 servo framesrevolution)Circu

Prefaceii C141-E057-01ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alertmessage consists

4.7 Servo ControlC141-E057-01EN 4-17(2) Servo burst capture circuitThe servo burst capture circuit reproduces signals (position signals) that indicat

Theory of Device Operation4-18 C141-E057-01EN4.7.2 Data-surface servo formatFigure 4.7 describes the physical layout of the servo frame. The three ar

4.7 Servo ControlC141-E057-01EN 4-19(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2) Servo ma

Theory of Device Operation4-20 C141-E057-01ENd) If the head is stopped at the reference cylinder from there. Track followingcontrol starts.(2) Seek o

4.7 Servo ControlC141-E057-01EN 4-21d) During phase switching, the spindle motor starts rotating in low speed, andgenerates a counter electromotive f

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C141-E057-01EN 5-1CHAPTER 5 Interface5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA Feature Set5.6 Timi

Interface5-2 C141-E057-01EN5.1 Physical Interface5.1.1 Interface signalsFigure 5.1 shows the interface signals.INTRQ: INTERRUPT REQUESTIOCS16-: 16-BIT

5.1 Physical InterfaceC141-E057-01EN 5-35.1.2 Signal assignment on the connectorTable 5.1 shows the signal assignment on the interface connector.Tabl

Interface5-4 C141-E057-01EN[signal][I/O][Description]ENCSELIThis signal is used to set master/slave using the CSEL signal (pin 28).Pins A and C Open:

PrefaceC141-E057-01EN iiiLiability Exception“Disk drive defects” refers to defects that involve adjustment, repair, orreplacement.Fujitsu is not liabl

5.1 Physical InterfaceC141-E057-01EN 5-5[signal][I/O][Description]IOCS16-OThis signal indicates 16-bit data bus is addressed in PIO data transfer.Thi

Interface5-6 C141-E057-01EN[signal][I/O][Description]DMARQOThis signal is used for DMA transfer between the host system andthe device. The device ass

5.2 Logical InterfaceC141-E057-01EN 5-75.2.1 I/O registersCommunication between the host system and the device is done through input-output (I/O) reg

Interface5-8 C141-E057-01EN5.2.2 Command block registers(1) Data register (X’1F0’)The Data register is a 16-bit register for data block transfer betwe

5.2 Logical InterfaceC141-E057-01EN 5-9[Diagnostic code]X’01’:No Error Detected.X’02’:HDC Register Compare ErrorX’03’:Data Buffer Compare Error.X’05’

Interface5-10 C141-E057-01EN(6) Cylinder Low register (X’1F4’)The contents of this register indicates low-order 8 bits of the starting cylinderaddress

5.2 Logical InterfaceC141-E057-01EN 5-11(9) Status register (X’1F7’)The contents of this register indicate the status of the device. The contents of

Interface5-12 C141-E057-01EN- Bit 5:The Device Write Fault (DF) bit. This bit indicates that a device fault(write fault) condition has been detected.

5.3 Host CommandsC141-E057-01EN 5-135.2.3 Control block registers(1) Alternate Status register (X’3F6’)The Alternate Status register contains the sam

Interface5-14 C141-E057-01ENWhen the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the datatransfer) and the host system writes to the co

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5.3 Host CommandsC141-E057-01EN 5-15Table 5.3 Command code and parameters (2 of 2)Command code (Bit)Parameters used7 6 5 4 3 2 1 0 FR SC SN CY DHIDLE

Interface5-16 C141-E057-01ENY*: Necessary to set parameters under the LBA mode.N: Not necessary to set parameters (The parameter is ignored if it is s

5.3 Host CommandsC141-E057-01EN 5-17CM: Command register FR: Features registerDH: Device/Head register ST: Status registerCH: Cylinder High regi

Interface5-18 C141-E057-01ENCommand block registers contain the cylinder, the head, and the sector addressesof the sector (in the CHS mode) or the log

5.3 Host CommandsC141-E057-01EN 5-19The implementation of the READ MULTIPLE command is identical to that of theREAD SECTOR(S) command except that the

Interface5-20 C141-E057-01ENFigure 5.2 Execution example of READ MULTIPLE commandAt command issuance (I/O registers setting contents)1F7H(CM)1 1 0 0 0

5.3 Host CommandsC141-E057-01EN 5-21(3) READ DMA (X’C8’ or X’C9’)This command operates similarly to the READ SECTOR(S) command except forfollowing ev

Interface5-22 C141-E057-01ENAt command completion (I/O registers contents to be read)1F7H(ST)Status information1F6H(DH)×L×DVEnd head No. /LBA [MSB]1F5

5.3 Host CommandsC141-E057-01EN 5-23At command issuance (I/O registers setting contents)1F7H(CM)0 1 0 0 0 0 0 R1F6H(DH)×L×DVStart head No. /LBA [MSB]

Interface5-24 C141-E057-01ENThe data stored in the buffer, and CRC code and ECC bytes are written to the datafield of the corresponding sector(s). Upo