Fujitsu MB15F74UL User Manual

Browse online or download User Manual for Unknown Fujitsu MB15F74UL. Fujitsu MB15F74UL User's Manual [en]

  • Download
  • Add to my manuals
  • Print
  • Page
    / 26
  • Table of contents
  • BOOKMARKS
  • Rated. / 5. Based on customer reviews
Page view 0
DS04-21374-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual S
erial Input
PLL Frequency
Synthesizer
MB15F74UL
DESCRIPTION
The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectable by serial date. The pin assignments are the same as MB15F78UL. Fast locking is achieved for adopting
the new circuit.
The new package (BCC20) decreases a mount area of MB15F74UL more than 30% comparing with the former
BCC16 (for dual PLL) .
FEATURES
High frequency operation : RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max
Low power supply voltage : VCC = 2.7 to 3.6 V
Ultra low power supply current : I
CC = 9.0 mA Typ
(VCC = Vp = 3.0 V, Ta = +25 °C, SWIF = SWRF = 0 in IF/RF locking state)
(Continued)
PACKAGE
20-pad plastic BCC
(LCC-20P-M05)
Page view 0
1 2 3 4 5 6 ... 25 26

Summary of Contents

Page 1 - MB15F74UL

DS04-21374-1EFUJITSU SEMICONDUCTORDATA SHEETASSPDual Serial InputPLL Frequency SynthesizerMB15F74UL DESCRIPTIONThe Fujitsu MB15F74UL is a serial input

Page 2

MB15F74UL10• Prescaler Data Setting• Charge Pump Current Setting•LD/fout output Selectable Bit Setting• Phase Comparator Phase Switching Data Setting

Page 3

MB15F74UL113. Power Saving Mode (Intermittent Mode Control Circuit) The intermittent mode control circuit reduces the PLL power consumption.By settin

Page 4

MB15F74UL124. Serial Data Data Input TimingDivide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.Setting data

Page 5

MB15F74UL13 PHASE COMPARATOR OUTPUT WAVEFORM• LD Output LogicNotes : • Phase error detection range = −2π to +2π • Pulses on DoIF/RF signals during lo

Page 6

MB15F74UL14 TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN) 1000 pF1000 pF1000 pF1000 pF0.1 µFVpRFVCCRF50 Ω50 Ω50 ΩS.G.S.G.S.G.VpIFVCCIF0.1

Page 7

MB15F74UL15 TYPICAL CHARACTERISTICS1.fin input sensitivity101000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000VCC = 2.7 VVCC = 3.0 VVCC = 3.6 VSPE

Page 8

MB15F74UL162.OSCIN input sensitivityVCC = 2.7 VVCC = 3.0 VVCC = 3.6 VSPEC0 50 100 150 200 250 3000−10−20−30−40−5010SPECInput sensitivity vs. Input fre

Page 9

MB15F74UL173. RF-PLL Do output current • 1.5 mA mode• 6.0 mA modeVCC = Vp = 3.0 V10.00−10.01.0 3.00.0 2.0Charge pump output current IDO (mA) IDO − VDO

Page 10

MB15F74UL184.IF-PLL Do output current• 1.5 mA mode• 6.0 mA modeIDO − VDOCharge pump output current IDO (mA) Charge pump output voltage VDO (V) 10.00−1

Page 11

MB15F74UL195.fin input impedance866.25 Ω−916.31 Ω100 MHz76.5 Ω−319.2 Ω500 MHz31.078 Ω−152.46 Ω1 GHz1 : 2 : 3 : START 100.000 000 MHz STOP 2 000.000 00

Page 12

MB15F74UL2(Continued)• Direct power saving function : Power supply current in power saving mode Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = +25 °C) Max 10 µA

Page 13

MB15F74UL206. OSCIN input impedanceOSCIN input impedance15.882 kΩ−11.652 kΩ3 MHz3.924 kΩ−8.942 kΩ10 MHz286 Ω−2.5913 kΩ40 MHz1 : 2 : 3 : START 3.000 00

Page 14

MB15F74UL21 REFERENCE INFORMATION (for Lock-up Time, Phase Noise and Reference Leakage) (Continued)Test CircuitS.G.OSCINfinDoLPFVCOSpectrumAnalyzer7.

Page 15

MB15F74UL22(Continued)100.0050MHz2.00kHz/div99.99500MHz0 s2.0000000 msA Mkr x: 439.99764 µsy: 50.0009 MHz100.0050MHz2.00kHz/div99.99500MHz0 s2.000000

Page 16

MB15F74UL23 APPLICATION EXAMPLE1000 pF1000 pF1000 pF1000 pF0.1 µF3.0 V3.0 V3.0 V3.0 V0.1 µF0.1 µF0.1 µF1000 pFGND OSCIN DataClockPSRFVCCRFGNDRFXfinRFL

Page 17

MB15F74UL24 USAGE PRECAUTIONS (1) VCCRF, VpRF, VCCIF and VpIF must be equal voltage. Even if either RF-PLL or IF-PLL is not used, power must be suppl

Page 18

MB15F74UL25 PACKAGE DIMENSION20-pad plastic BCC (LCC-20P-M05) Dimensions in mm (inches)C2001 FUJITSU LIMITED C20056S-c-2-13.60±0.10(.142±.004)11161

Page 19

MB15F74ULFUJITSU LIMITEDAll Rights Reserved.The contents of this document are subject to change without notice. Customers are advised to consult with

Page 20

MB15F74UL3 PIN DESCRIPTIONPin no.Pin nameI/O Descriptions1finIF IPrescaler input pin for the IF-PLL.Connection to an external VCO should be AC couplin

Page 21

MB15F74UL4 BLOCK DIAGRAM(9)ClockDataLEPSRFXfinRFfinRFOSCINfinIFPSIFVCCIF GNDIFfpIFDoIFLDIFT1 T2T1 T2FCRFSWRFLDSDoRFORLD/foutLDfrIFfrRFfpIFfpRFfrIFfrRF

Page 22

MB15F74UL5 ABSOLUTE MAXIMUM RATINGSWARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,

Page 23

MB15F74UL6 * ELECTRICAL CHARACTERISTICS (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)(Continued)Parameter Symbol ConditionValueUnitMin Typ MaxPower s

Page 24

MB15F74UL7(Continued) (VCC = 2.7 V to 3.6 V, Ta = −40 °C to +85 °C)*1 : Conditions ; fosc = 12.8 MHz, Ta = +25 °C, SW = “L” in locking state.*2 : VCCI

Page 25

MB15F74UL8 FUNCTIONAL DESCRIPTION1. Pulse swallow functionfVCO = [ (P × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled os

Page 26 - FUJITSU LIMITED

MB15F74UL9 (2) Data setting•Binary 14-bit Programmable Reference Counter Data Setting Note : Divide ratio less than 3 is prohibited.•Binary 11-bit Pro

Comments to this Manuals

No comments