Fujitsu SPARC64 V User Manual

Fujitsu Limited4-1-1 KamikodanakaNahahara-ku, Kawasaki, 211-8588JapanSPARC JPS1 Implementation Supplement: Fujitsu SPARC64 VFujitsu LimitedRelease 1.

Release 1.0, 1 July 2002 F. Chapter Contents viiTLB Error Handling 195Handling of TLB Entry Errors 195Automatic Way Reduction of sTLB 196Handling of

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 898K_POINTER = TSB_Extension[63:14+N] 0 (VA[21+N:13] ⊕ TSB_Hash) 000064K_POINTER =

90 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002 X1: The contents of the context field of the D-MMU Tag Access

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 91 An fDTLB entry parity error is detected in a fDTLB lookup for an instruction operand a

92 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002F.10 Internal Registers and ASI operationsF.10.1 Accessing MMU Re

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 93F.10.4 I/D TLB Data In, Data Access, and Tag Read RegistersIMPL. DEP. #234: The replace

94 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002For fTLB, SPARC64 V implements a pseudo-LRU. For sTLB, LRU is use

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 95The MMU TLB data access address assignment and the purpose of the address on SPARC64 V

96 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002FIGURE F-2 Index number of set associative TLBsI/D MMU TLB Tag Ac

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 97I/D TSB Base RegistersIMPL. DEP. #236: The width of the TSB_Size field in the TSB Base

98 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002The specification of bits 24:0 in the SPARC64 V SFSR conforms to

viii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 99TABLE F-6 describes the field encoding for ISFSR.FT. Data <15> TM R/W Translatio

100 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002ISFSR is updated either upon a occurrence of a fast_instruction_

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 101Data <46> MK R/W Marked UE. On SPARC64 V, all uncorrectable errors are reported

102 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002TABLE F-9 defines the encoding of the FT<6:0> field. Data

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit103Multiple bits of DSFSR.FT may be set by a trap as long as the cause of the trap matches

104 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002F.11 MMU BypassOn SPARC64 V, two additional ASIs are supported a

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 105F.11.10 TLB Replacement PolicyAutomatic TLB Replacement RuleOn an automatic replacemen

106 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002 sTLB entry update data: New sTLB entry data is designated in st

F.APPENDIX 107GAssembly Language SyntaxPlease refer to Appendix G of Commonality.

108 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

1F.CHAPTER1Overview1.1 Navigating the SPARC64 V Implementation SupplementWe suggest that you approach this Implementation Supplement SPARC Joint Progr

F.APPENDIX 109HSoftware ConsiderationsPlease refer to Appendix H of Commonality.

110 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 111IExtending the SPARC V9 ArchitecturePlease refer to Appendix I of Commonality.

112 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 113JChanges from SPARC V8 to SPARC V9Please refer to Appendix K of Commonality.

114 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 115KProgramming with the Memory ModelsPlease refer to Appendix J of Commonality.

116 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX117LAddress Space IdentifiersEvery load or store address in a SPARC V9 processor has an 8-bit Address Space Identifier (ASI) appended to the

118 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20024516ASI_DCU_CONTROL_REG (ASI_DCUCR)RW00 224516ASI_MEMORY_CONTRO

2 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20021.3 The SPARC64 V processorThe SPARC64 V processor is a high-perfo

Release 1.0, 1 July 2002 F. Chapter L Address Space Identifiers 119L.3.2 Special Memory Access ASIsPlease refer to Section L.3.3 in Commonality. In ad

120 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002ASI 4F16 (ASI_SCRATCH_REGx)SPARC64 V provides eight of 64-bit re

Release 1.0, 1 July 2002 F. Chapter L Address Space Identifiers 121n = 2 (4-byte alignment): LDDF_mem_address_not_aligned exception is generated.n ≤

122 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20023. When the LBSY on the SB is changed, LBSY change information i

Release 1.0, 1 July 2002 F. Chapter L Address Space Identifiers 123BSTW Control Register (ASI_C_BSTW0, ASI_C_BSTW1)The BSTW control register designate

124 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Last Barrier Synchronization Status Read (ASI_LBSYR0, ASI_LBSYR1

F.APPENDIX 125MCache OrganizationThis appendix describes SPARC64 V cache organization in the following sections: Cache Types on page 125 Cache Coheren

126 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002M.1.1 Level-1 Instruction Cache (L1I Cache)TABLE M-1 shows the c

Release 1.0, 1 July 2002 F. Chapter M Cache Organization 127M.1.2 Level-1 Data Cache (L1D Cache)The level-1 data cache is a writeback cache. Its chara

128 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002M.2 Cache Coherency ProtocolsThe CPU uses the UPA MOESI cache-co

Release 1.0, 1 July 2002 F. Chapter 1 Overview 31. Advanced RAS features for caches Strong cache error protection: ECC protection for D1 (Data level 1

Release 1.0, 1 July 2002 F. Chapter M Cache Organization 1291. The opcode of the instructions should be ldda, ldxa, lddfa, stda, stxa, or stdfa. Other

130 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002M.3.2 Level-2 Cache Control Register (ASI_L2_CTRL)ASI_L2_CTRL is

Release 1.0, 1 July 2002 F. Chapter M Cache Organization 131ASI_L2_DIAG_TAG_READ works in concert with ASI_L2_DIAG_TAG_READ_REG. A read to ASI_L2_DIAG

132 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 133NInterrupt HandlingInterrupt handling in SPARC64 V is described in these sections: Interrupt Dispatch on page 133 Interrupt Receive on p

134 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002read ASI_INTR_DISPATCH_STATUSError(begin atomic sequence) PSTATE

Release 1.0, 1 July 2002 F. Chapter N Interrupt Handling 135N.2 Interrupt ReceiveWhen an interrupt packet is received, eight interrupt data registers

136 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002N.3 Interrupt Global RegistersPlease refer to Section N.3. of Co

F.APPENDIX 137OReset, RED_state, and error_stateThe appendix contains these sections: Reset Types on page 137 RED_state and error_state on page 139 Pr

138 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20023. The UPA_RESET_L pin is deasserted. The processor enters RED_s

4 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002 Asynchronous data error (ADE) trap for additional errors: Relaxed

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 139O.2 RED_state and error_stateFIGURE O-1 illustrates the processor state tra

140 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002O.2.1 RED_stateOnce the processor enters RED_state for any reaso

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 141O.2.3 CPU Fatal Error stateThe processor enters CPU fatal error state when

142 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002 TLECLE0/ Copied from CLE0/ UnchangedCopied from CLEUnchangedTBA

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 143TABLE O-2 ASR State after Reset and in RED_state ASRName POR11.Hard POR occ

144 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20024A 00 UPA_CONFIGWB_SWRI_SINT_SUC_SAMMCAPCLK_MODESCIQ1SCIQ0UPC_CA

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 14558 20 DMMU_SFARUnknown/Unchanged Unchanged58 28 DMMU_TSB_BASEUnknown/Unchan

146 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002O.3.1 Operating Status Register (OPSR)OPSR is the control regist

Release 1.0, 1 July 2002 F. Chapter O Reset, RED_state, and error_state 147O.3.2 Hardware Power-On Reset SequenceTo be defined later.O.3.3 Firmware In

148 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Release 1.0, 1 July 2002 F. Chapter 1 Overview 5FIGURE 1-1 SPARC64 V Major UnitsExtended UPA BusUPA interface logicMoveIn bufferMoveOut bufferSX-UnitU

F.APPENDIX 149PError HandlingThis appendix describes processor behavior to a programmer writing operating system, firmware, and recovery code for SPAR

150 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002When the CPU detects the fatal error, the CPU enters FATAL error

Release 1.0, 1 July 2002 F. Chapter P Error Handling 151 Otherwise, an error exception is generated and the damaged instruction is executed as when AS

152 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002When the resource with the error is used, the program cannot con

Release 1.0, 1 July 2002 F. Chapter P Error Handling 153 DegradationSPARC64 V can isolate an internal hardware resource that generates frequent errors

154 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002P.2.2 Summary of Actions Upon Error DetectionTABLE P-2 summarize

Release 1.0, 1 July 2002 F. Chapter P Error Handling155Action upon the error detection1. CPU enters CPU fatal state.2. CPU informs the system of fatal

156SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002tt (trap type) 1 (RED_state)2 (RED_state)ADE: 4016DAE: 3216IAE: 0A

Release 1.0, 1 July 2002 F. Chapter P Error Handling157P.2.3 Extent of Automatic Source Data Correction for Correctable ErrorUpon detection of the fol

158SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002 When a hardware unit first detects an uncorrected error in the ca

6 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20021.3.2 Instruction Control Unit (IU)The IU predicts the instruction

Release 1.0, 1 July 2002 F. Chapter P Error Handling159The ERROR_MARK_ID (14 bits wide) identifies the error source. The hardware unit that detects th

160SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002Difference Between Error Marking on SPARC64 IV and SPARC64 VTABLE

Release 1.0, 1 July 2002 F. Chapter P Error Handling161P.2.5ASI_EIDRThe ASI_EIDR register designates the source ID in the ERROR_MARK_ID of the CPU. P.

162SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 20021 WEAK_ED RW Weak Error Detection. Controls whether the detection

Release 1.0, 1 July 2002 F. Chapter P Error Handling163P.3 Fatal Error and error_state Transition ErrorP.3.1 ASI_STCHG_ERROR_INFOThe ASI_STCHG_ERROR_I

164SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.3.2 Fatal Error Types FE_UPA_ADDR_UNCORRECTED_ERROR — An uncorre

Release 1.0, 1 July 2002 F. Chapter P Error Handling165 Ideal specification (not implemented)The EE_OTHER bit is specified in ASI_STCHG_ERROR_INFO bit

166SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 200222 IAUG_CRE R Uncorrectable error in any of the following:(IA) ASI

Release 1.0, 1 July 2002 F. Chapter P Error Handling16715 AUG_SDC R System data corruption. Indicates the occurrence of the following system data corr

168SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.4.2 Action of async_data_error (ADE) TrapThe single-ADE trap and

Release 1.0, 1 July 2002 F. Chapter 1 Overview 71.3.4 Storage Unit (SU)The SU handles all sourcing and sinking of data for load and store instructions

Release 1.0, 1 July 2002 F. Chapter P Error Handling169The following actions are executed in this order:a. State transitionif (TL=MAXTL), the CPU ente

170SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002Errors in registers other than those listed above and any errors i

Release 1.0, 1 July 2002 F. Chapter P Error Handling171TABLE P-14 defines each instruction end-method after an ADE trap.P.4.4 Expected Software Handli

172SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002voidexpected_software_handling_of_ADE_trap(){/* Only %r0-%r7 can b

Release 1.0, 1 July 2002 F. Chapter P Error Handling173causes the data_access_error trap when its tag matches at the DTLB reference for address transl

174SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.7 Restrainable ErrorsThis section describes the registers—ASI_AS

Release 1.0, 1 July 2002 F. Chapter P Error Handling175 If the Prio_U2 column for the error shown in the table row is blank, the error is never record

176SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 20023 UE_DST_BETO RW1C Disrupting store UPA bus error or timeout. Indi

Release 1.0, 1 July 2002 F. Chapter P Error Handling177P.7.2 ASI_ASYNC_FAULT_ADDR_D1 TABLE P-16 describes the fields of the ASI_ASYNC_FAULT_ADDR_D1 re

178SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.7.3 ASI_ASYNC_FAULT_ADDR_U2The ASI_ASYNC_FAULT_ADDR_U2 register

8 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20021.3.5 Secondary Cache and External Access Unit (SXU)The SXU contro

Release 1.0, 1 July 2002 F. Chapter P Error Handling179P.7.4 Expected Software Handling of Restrainable ErrorsError recording and information is expec

180SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002b. Write the U2 cache line with the CE detection to memory either

Release 1.0, 1 July 2002 F. Chapter P Error Handling181P.8 Handling of Internal Register ErrorsThis section describes error handling for the following

182SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.8.2 ASR Error Handling The terminology used in TABLE P-19 is def

Release 1.0, 1 July 2002 F. Chapter P Error Handling183P.8.3 ASI Register Error HandlingThe terminology used in TABLE P-20 is defined as follows: 5 PC

184SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002Error Detect ConditionAlways Error is always checked.AUG always Er

Release 1.0, 1 July 2002 F. Chapter P Error Handling185Error Type error_state error_state transition error.(I)AUG_xxxx The error is indicated by ASI_U

186SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002TABLE P-20 shows the handling of ASI register errors.TABLE P-20Han

Release 1.0, 1 July 2002 F. Chapter P Error Handling18758163016DMMU_TAG_ACCESS RW Parity LDXA #DIUG_TSBPW (WotherD)58163816DMMU_VA_WATCHPOINT RW Parit

188SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002SPARC64 V Implementation and the Ideal SpecificationIn the table o

Release 1.0, 1 July 2002 F. Chapter 2Copyright 2002 Sun Microsystems, Inc., 901 San Antonio Road, Palo Alto, California 94303 U.S.A. All rights rese

9F.CHAPTER2DefinitionsThis chapter defines concepts unique to the SPARC64 V, the Fujitsu implementation of SPARC JPS1. For definition of terms that ar

Release 1.0, 1 July 2002 F. Chapter P Error Handling189When a parity error is detected in a D1 cache tag entry or in a D1 cache tag copy entry, hardwa

190SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.9.2 Handling of an I1 Cache Data ErrorI1 cache data is protected

Release 1.0, 1 July 2002 F. Chapter P Error Handling191Marked Uncorrectable Error in D1 Cache DataWhen a marked uncorrectable error (UE) in D1 cache d

192SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002P.9.4 Handling of a U2 Cache Data ErrorU2 cache data is protected

Release 1.0, 1 July 2002 F. Chapter P Error Handling193doubleword and its ECC in the read data and those in the source U2 cache line are changed to ma

194SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 20022. Otherwise: All entries in I1 cache way W are invalidated and th

Release 1.0, 1 July 2002 F. Chapter P Error Handling1952. Otherwise: All entries in available U2 cache ways, including way W, are invalidated to retai

196SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002When a parity error is detected in an ITLB entry when an LDXA inst

Release 1.0, 1 July 2002 F. Chapter P Error Handling197sTLB Way ReductionWhen a way reduction condition is recognized for the sTLB way W (W =0 or 1),

198SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 2002 Raw (unmarked) uncorrectable error (multibit error) Marked uncorr

10 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002instruction retired Term applied to an instruction when all machi

Release 1.0, 1 July 2002 F. Chapter P Error Handling199 Incoming noncacheable data fetched by an instruction fetch. When a UE is detected in such data

200 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 201QPerformance InstrumentationThis appendix describes and specifies performance monitors that have been implemented in the SPARC64 V proce

202 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002/* clear pics without altering sl/su values */pic_init = 0x0;pcr

Release 1.0, 1 July 2002 F. Chapter Q Performance Instrumentation 203for(i=0; i<=pcr.nc; i++) {/* assume rest of pcr data has been preserved */pcr.

204 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Q.2.1 Instruction StatisticsInstruction statistics counters can

Release 1.0, 1 July 2002 F. Chapter Q Performance Instrumentation 205●Instruction Count (instruction_counts)Counts the number of committed instruction

206 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002●Prefetch Instruction Count (prefetch_instructions)Counts the co

Release 1.0, 1 July 2002 F. Chapter Q Performance Instrumentation 207●Software Instruction Trap (trap_trap_inst)Counts the occurrences of Tcc instruct

208 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Q.2.4 Cache Event Counters●I1 Cache Miss Count (if_r_iu_req_mi_g

Release 1.0, 1 July 2002 F. Chapter 2 Definitions 11in parallel. When instructions are committed, results in renamed registers are posted to the archi

Release 1.0, 1 July 2002 F. Chapter Q Performance Instrumentation 209●L2 Cache Miss Count by Demand Access (sx_miss_count_dm)Counts the occurrences of

210 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Q.2.5 UPA Event CountersUPA event counters count the number of S

Release 1.0, 1 July 2002 F. Chapter Q Performance Instrumentation 211Q.2.6 Miscellaneous Counters●Barrier-Assist ASI Read Count (asi_rd_bar)Counts the

212 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 213RUPA Programmer’s ModelThis chapter describes the programmers model of the UPA interface of the SPARC64 V. The registers for the UPA int

214 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002R.2 UPA PortID RegisterThe UPA PortID Register is a standard rea

Release 1.0, 1 July 2002 F. Chapter R UPA Programmer’s Model 215R.3 UPA Config RegisterThe UPA Config Register is an implementation-specific ASI read-

216 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 200258:57 WRI_S Specify the size of maximum outstanding WRI packet a

Release 1.0, 1 July 2002 F. Chapter R UPA Programmer’s Model 21729:23 PCON Processor Configuration. Separated into PCON<6:4> and PCON<3:0>

218 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

12 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 219SSummary of Differences between SPARC64 V and UltraSPARC-IIIThe following table summarizes differences between SPARC64 V and UltraSPARC-

220 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Floating-point subnormal handlingIn general, SPARC64V does not h

Release 1.0, 1 July 2002 F. Chapter S Summary of Differences between SPARC64 V and UltraSPARC-III 221Error status ASI 4C16/0816 (ASI_UGESR): SPARC64V

222 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

223F.CHAPTERBibliographyGeneral ReferencesPlease refer to Bibliography in Commonality.

224 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

225F.CHAPTERIndex AA_UGEcategories152error detection action155error detection mask154specification of151address mask (AM) field of PSTATE register49,

226 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002ASI_C_BSTW0123ASI_C_BSTW1123ASI_C_LBSTWBUSY123ASI_C_LBSYR0122ASI

Release 1.0, 1 July 2002 F. Chapter Index 227ASI_INTR_W133, 134ASI_ITLB_DATA_ACCESS196ASI_ITLB_TAG_ACCESS196ASI_L2_CTRL130ASI_L2_DIAG_TAG131ASI_L2_DI

228 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002compare and swap37Bbarrier assist121ASI read/write accesses, cou

13F.CHAPTER3Architectural OverviewPlease refer to Chapter 3 in the Commonality section of SPARC Joint Programming Specification.

Release 1.0, 1 July 2002 F. Chapter Index 229level-2characteristics125control register130tag read130unified127use2snooping140synchronizing42unifiedch

230 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002error detection mask154reporting151datacacheabledoubleword error

Release 1.0, 1 July 2002 F. Chapter Index 231dispatch (instruction)9disrupting traps17, 37distributionnonspeculative10speculative11DMMUaccess bypassi

232 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002ECC_error exception46, 153, 155, 180ee_opsr164ee_second_watch_do

Release 1.0, 1 July 2002 F. Chapter Index 233privileged_action79statistics monitoring206–207unfinished_FPop62, 65execute_state140executed, definition

234 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002FMADDs instruction50FMSUB instruction30, 45FMSUBd instruction50F

Release 1.0, 1 July 2002 F. Chapter Index 235IMMUinternal register (ASI_MCNTL)92registers accessed92Synchronous Fault Status Register97IMMU_DEMAP reg

236 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002implementation-dependent (IMPDEP2)30implementation-dependent (IM

Release 1.0, 1 July 2002 F. Chapter Index 237JMPL instruction29, 53JPS1_TSBP mode93JTAG command91, 164, 189LLBSY control register122LDD instruction37

238 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002store order (STO)75TSO41, 42MEMORY_CONTROL register186mmask fiel

14 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Release 1.0, 1 July 2002 F. Chapter Index 239partial ordering, specification56partial store instructionUPA transaction57watchpoint exceptions57partia

240 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002PRIMARY_CONTEXT register186privileged registers19privileged_acti

Release 1.0, 1 July 2002 F. Chapter Index 241clock-tick (TICK)73current window pointer (CWP)75Data Cache Unit Control (DCUCR)23LBSY control122other w

242 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002scandefinition11ring11sDTLB77, 85, 90SECONDARY_CONTEXT register1

Release 1.0, 1 July 2002 F. Chapter Index 243TTag Access Register96Tcc instruction, counting207TICK register19, 73TICK_COMPARE register183TL register

244 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002way reduction194uDTLB10, 85, 90UE_RAW_D1$INSD error191UE_RAW_L2$

15F.CHAPTER4Data FormatsPlease refer to Chapter 4, Data Formats in Commonality.

16 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

17F.CHAPTER5RegistersThe SPARC64 V processor includes two types of registers: general-purpose—that is, working, data, control/status—and ASI registers

18 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20025.1.7 Floating-Point State Register (FSR)Please refer to Section

3 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Release 1.0, 1 July 2002 F. Chapter 5 Registers 19else if (<FPop commits with IEEE_754_exception>)<set one bit in the CEXC field as supplied

20 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Note – Spurious setting of the PSTATE.RED bit by privileged softw

Release 1.0, 1 July 2002 F. Chapter 5 Registers 21The Performance Control Register in SPARC64 V is illustrated in FIGURE 5-1 and described in TABLE 5-

22 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Performance Instrumentation Counter (PIC) Register (ASR 17)The PI

Release 1.0, 1 July 2002 F. Chapter 5 Registers 23After a power-on reset (POR), all fields of DCUCR, including implementation-dependent fields, are se

24 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Data Watchpoint RegistersNo implementation-dependent feature of S

25F.CHAPTER6InstructionsThis chapter presents SPARC64 V implementation-specific instruction details and the processor pipeline information in these su

26SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V• Release 1.0, 1 July 20021. If a memory operation y resolves to a volatile memory address (l

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 276.1.3 Syncing InstructionsSPARC64 V has instructions, called syncing instructions, that stop exec

28 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20026.2 Instruction Formats and FieldsInstructions are encoded in fiv

iF.CHAPTERContents1. Overview 1Navigating the SPARC64 V Implementation Supplement 1Fonts and Notational Conventions 1The SPARC64 V processor 2Componen

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 29Since size= 00 is not IMPDEP2B and since size= 11 assumed quad operations but is not implemented

30 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002SPARC64 V implements JMPL and CALL return prediction hardware in

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 316.4 Processor PipelineThe pipeline of SPARC64 V consists of fifteen stages, shown in FIGURE 6-2.

32 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002FIGURE 6-2 SPARC64 V PipelineIAITIMIBIRDPBXTsMsBsRsUWEPsBRHISiTLB

Release 1.0, 1 July 2002 F. Chapter 6 Instructions 336.4.2 Issue Stages E (Entry) — Instructions are passed from fetch stages. D (Decode) — Assign res

34 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Execution Stages for Cache AccessMemory access requests are passe

35F.CHAPTER7TrapsPlease refer to Chapter 7 of Commonality. Section numbers in this chapter correspond to those in Chapter 7 of Commonality.This chapte

36 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20027.1.1 RED_stateRED_state Trap TableThe RED_state trap vector is l

Release 1.0, 1 July 2002 F. Chapter 7 Traps 37Although the standard behavior of the CPU upon an entry into error_state is to internally generate a wat

38 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20027.3 Trap ControlPlease refer to Section 7.3 of Commonality.7.3.1

ii SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Floating-Point Deferred-Trap Queue (FQ) 24IU Deferred-Trap Queue

Release 1.0, 1 July 2002 F. Chapter 7 Traps 397.4.4 Details of Supported TrapsPlease refer to Section 7.4.4 in Commonality.SPARC64 V Implementation-Sp

40 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002 Uncorrectable errors in the internal architecture registers (gen

41F.CHAPTER8Memory ModelsThe SPARC V9 architecture is a model that specifies the behavior observable by software on SPARC V9 systems. Therefore, acces

42 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20028.1 OverviewNote – The words “hardware memory model” denote the u

Release 1.0, 1 July 2002 F. Chapter 8 Memory Models 43corresponding locations in all instruction caches; references to any instruction cache cause cor

44 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 45AInstruction Definitions: SPARC64 V ExtensionsThis appendix describes the SPARC64 V-specific implementation of the instructions in Append

46 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20024. A description of the features, restrictions, and exception-cau

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 47A.4 Block Load and Store Instructions (VIS I)The following notes

48 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 20024. The block store with commit instruction always stores the oper

Release 1.0, 1 July 2002 F. Chapter Contents iii SPARC JPS1 Implementation-Dependent Traps 398. Memory Models 41Overview 42SPARC V9 Memory Model 42Mo

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 49A.12 Call and LinkSPARC64 V clears the upper 32 bits of the PC v

50 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002A.24.1 Floating-Point Multiply-Add/SubtractSPARC64 V uses IMPDEP2

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 51DescriptionThe Floating-point Multiply-Add instructions multiply

52 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002detects any conditions for an unfinished_FPop trap, the Floating-

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 53Programming Note – The Multiply Add/Subtract instructions are en

54 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002A.30 Load Quadword, Atomic [Physical]The Load Quadword ASIs in th

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 55 TTE.NFO = 0 TTE.CP = 1 TTE.CV = 0 TTE.E = 0 TTE.P = 1 TTE.W

56 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002DescriptionThe memory barrier instruction, MEMBAR, has two comple

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 57A.42 Partial Store (VIS I)Please refer A.42 in Commonality for g

58 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002TABLE A-7 describes prefetch variants implemented in SPARC64 V. A

iv SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002D. Formal Specification of the Memory Models 81E. Opcode Maps 83F

Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 59A.70 Write State RegisterIn SPARC64 V, a WRPCR instruction will

60 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 61BIEEE Std 754-1985 Requirements for SPARC V9The IEEE Std 754-1985 floating-point standard contains a number of implementation dependencie

62 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002SPARC64 V floating-point hardware has its specific range of compu

Release 1.0, 1 July 2002 F. Chapter B IEEE Std 754-1985 Requirements for SPARC V9 63Implementation Note – Detecting the exact boundary conditions requ

64 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002Pessimistic ZeroIf a condition in TABLE B-3 is true, SPARC64 V ge

Release 1.0, 1 July 2002 F. Chapter B IEEE Std 754-1985 Requirements for SPARC V9 65 Pessimistic OverflowIf a condition in TABLE B-4 is true, SPARC64

66 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002summarizes the behavior of SPARC64 V floating-point hardware depe

Release 1.0, 1 July 2002 F. Chapter B IEEE Std 754-1985 Requirements for SPARC V9 67TABLE B-6 describes how SPARC64 V behaves when FSR.NS = 1 (nonstan

68 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

Release 1.0, 1 July 2002 F. Chapter Contents vLevel-1 Data Cache (L1D Cache) 127Level-2 Unified Cache (L2 Cache) 127Cache Coherency Protocols 128Cach

F.APPENDIX 69CImplementation DependenciesThis appendix summarizes implementation dependencies. In SPARC V9 and SPARC JPS1, the notation “IMPL. DEP. #n

70 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002C.2 Hardware CharacteristicsPlease refer to Section C.2 of Common

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 719 RDASR/WRASR privileged statusSee A.50 and A.70 in Commonality for details of imp

72 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 200232 Deferred trapsSPARC64 V signals a deferred trap in a few of it

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 7342 FLUSH instructionSPARC64 V implements the FLUSH instruction in hardware.—43 Res

74 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002106 IMPDEPn instructionsSPARC64 V uses the IMPDEP2 opcode for the

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 75119 Unimplemented values for PSTATE.MMWriting 112 into PSTATE.MM causes the machin

76 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002206 SHUTDOWN instructionIn privileged mode the SHUTDOWN instructi

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 77218async_data_errorasync_data_error trap is implemented in SPARC64 V, using tt =40

78 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002227 TSB number of entriesSPARC64 V supports a maximum of 16 milli

vi SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002error_state Transition Error 150Urgent Error 150Restrainable Erro

Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 79240 DCU Control Register bits 47:41SPARC64 V uses bit 41 for WEAK_SPCA, which enab

80 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002252 DCUCR.DC (Data Cache Enable)SPARC64 V does not implement DCUC

F.APPENDIX 81DFormal Specification of the Memory ModelsPlease refer to Appendix D of Commonality.

82 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 83EOpcode MapsPlease refer to Appendix E in Commonality. TABLE E-1 lists the opcode map for the SPARC64 V IMPDEP2 instruction. TABLE E-1 IM

84 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002

F.APPENDIX 85FMemory Management UnitThe Memory Management Unit (MMU) architecture of SPARC64 V conforms to the MMU architecture defined in Appendix F

86 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002The micro-TLBs are coherent to main TLBs and are not visible to s

Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 87The physical address length to be passed to the UPA interface is 41 bits or 43 bits, as

88 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002F.3.3 TSB OrganizationIMPL. DEP. #227: The maximum number of entr