Fujitsu SPARC64 V manuals

Fujitsu SPARC64 V User Manual (255 pages)

Brand: Fujitsu | Category: Unknown | Size: 2.55 MB |

English

Table of contents

SPARC JPS1

1

Implementation Supplement:

1

Fujitsu SPARC64 V

1

Contents

4

Overview

12

1.3 The SPARC64 V processor

13

1.3.1 Component Overview

15

Commit stack entry

16

Reservation stations

16

1.3.3 Execution Unit (EU)

17

1.3.4 Storage Unit (SU)

18

TABLE 1-4

19

Definitions

20

Architectural Overview

24

Data Formats

26

5.2 Privileged Registers

30

5.2.9 Version (VER) Register

31

FIGURE 5-1

32

TABLE 5-2

32

Counter Overflow

33

DCUCR Description

34

5.2.14 IU Deferred-Trap Queue

35

Instructions

36

6.1.2 Instruction Prefetch

37

6.1.3 Syncing Instructions

38

Format 5 (op = 2, op3 = 37

39

6.3 Instruction Categories

40

IA IT IM IB IR

42

EDPBX UW

42

Ps Ts Ms Bs Rs

42

Instruction Buffer

43

6.4.2 Issue Stages

44

6.4.3 Execution Stages

44

6.4.4 Completion Stages

45

7.1.1 RED_state

47

7.1.2 error_state

47

7.2 Trap Categories

48

7.3 Trap Control

49

7.5 Trap Processing

50

Memory Models

52

8.1 Overview

53

8.4 SPARC V9 Memory Model

53

Instruction Definitions:

56

SPARC64 V Extensions

56

Ordered/

58

Out-of-Orderfirst next

58

Exceptions fp_disabled

59

Exceptions

60

Format (5)

61

Description

62

Non-Trapping cexc When

63

Non-Trapping aexc When

63

Format (3) LDDA

65

A.35 Memory Barrier

66

A.42 Partial Store (VIS I)

68

A.49 Prefetch Data

68

A.51 Read State Register

69

A.70 SHUTDOWN (VIS I)

69

A.70 Write State Register

70

A.71 Deprecated Instructions

70

SPARC V9

72

Exception (ftt=

73

Implementation Note –

74

Pessimistic Zero

75

Pessimistic Overflow

76

TABLE B-6

78

Implementation Dependencies

80

C.2 Hardware Characteristics

81

TABLE C-1

82

Commonality

92

Opcode Maps

94

Memory Management Unit

96

IMPL. DEP. #223

97

IMPL DEP

97

IMPL. DEP. #224

97

IMPL. DEP. #238

98

IMPL. DEP. #225

98

IMPL. DEP. #242

98

IMPL. DEP. #226

98

(VA[24+N:16] ⊕ TSB_Hash)

99

(VA[21+N:13] ⊕ TSB_Hash)

100

(VA[24+N:16] ⊕

100

IMPL. DEP. #231

102

IMPL. DEP. #232

102

IMPL. DEP. #117

102

IMPL. DEP. #239

103

Format of

103

IMPL. DEP. #233

103

Registers

104

IMPL. DEP. #235

105

SPARC64 V are shown in

106

FIGURE F-2

107

I/D TSB Base Registers

108

Bit Description

109

ISFSR.FT

110

ISFSR Update Policy

111

TABLE F-8

112

TABLE F-9

113

Update Policy

114

F.11 MMU Bypass

115

Assembly Language Syntax

118

Software Considerations

120

Extending the SPARC V9

122

Architecture

122

F.APPENDIX

124

Programming with the Memory

126

Address Space Identifiers

128

TABLE L-1

129

ASI_SERIAL_ID

130

Block Load and Store ASIs

131

Partial Store ASIs

131

L.4.1 Interface Definition

132

L.4.2 ASI Registers

133

Programming Note –

134

ASI_C_BSTW

134

ASI_C_LBSTWBUSY

134

ASI_LBSYR1)

135

Cache Organization

136

L1D Cache Characteristics

138

L2 Cache Characteristics

138

M.2 Cache Coherency Protocols

139

ASI_FLUSH_L1I

140

Reserved

141

(ASI_L2_DIAG_TAG_READ_REG)

142

Interrupt Handling

144

FIGURE N-1

145

N.2 Interrupt Receive

146

O.1 Reset Types

148

O.1.2 Watchdog Reset (WDR)

149

O.2 RED_state and error_state

150

O.2.1 RED_state

151

O.2.2 error_state

151

RED_state

152

To be defined later

158

Error Handling

160

P.1.3 Urgent Error

161

P.1.4 Restrainable Error

163

P.2 Action and Error Control

164

TABLE P-2

165

Fatal Error (FE)

165

Error State Transition

165

Correctable Error

168

Format of Error-Marked Data

169

ERROR_MARK_ID Set by CPU

170

SPARC64 V

171

ASI_EIDR

172

ASI_ERROR_CONTROL

172

Transition Error

174

P.3.2 Fatal Error Types

175

P.4 Urgent Error

176

ASI_UGESR

177

Bit Description (4 of 4)

179

TABLE P-12

180

Exceptions

181

Instruction End-Method After

182

Exception

182

P.5 Instruction Access Errors

184

P.6 Data Access Errors

184

P.7 Restrainable Errors

185

CE_INCOMED

186

ASI_ASYNC_FAULT_STATUS

187

) Bit Description

188

P.7.3 ASI_ASYNC_FAULT_ADDR_U2

189

P.7.4 Expected

190

ECC_error

191

Registers)

192

P.8.2 ASR Error Handling

193

is defined as follows:

194

The terminology used in

194

(2 of 3)

195

(3 of 3)

196

• Release 1.0, 1 July 2002

197

TABLE P-20

197

P.9 Cache Error Handling

199

Line Writeback

202

ASI_AFSR.UE_RAW_L2$FILL

203

U2 Cache

204

D1 Cache Way Reduction

205

U2 Cache Way Reduction

205

P.10 TLB Error Handling

206

Translation

207

Way Reduction Condition

207

ASI_AFSR.DG_L1$U2$STLB

208

ASI_UGESR.AUG_SDC

208

Data Bus

209

Performance Instrumentation

212

Counter Stop and Read

213

TABLE Q-1

214

Q.2.1 Instruction Statistics

215

Q.2.2 Trap-Related Statistics

217

Q.2.3 MMU Event Counters

218

Q.2.4 Cache Event Counters

219

Q.2.5 UPA Event Counters

221

Q.2.6 Miscellaneous Counters

222

UPA Programmer’s Model

224

R.2 UPA PortID Register

225

R.3 UPA Config Register

226

TABLE R-3

227

Bits Field Description

227

SPARC64 V and UltraSPARC-III

230

Bibliography

234

F.CHAPTER

236

LDDF_mem_address_not_aligned

248

LDQF_mem_address_not_aligned

248

STQF_mem_address_not_aligned

253

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