Fujitsu MPD3XXXAH User Manual download pdf (Page 144)

C141-E072-01EN 5 - 77

3) The device shall stop generating DSTROBE edges within t

RFS

of the host negating

HDMARDY-.

4) If the host negates HDMARDY- within t

SR

after the device has generated a

DSTROBE edge, then the host shall be prepared to receive zero or one additional data

words. If the host negates HDMARDY- greater than t

SR

after the device has

generated a DSTROBE edge, then the host shall be prepared to receive zero, one or

two additional data words. The additional data words are a result of cable round trip

delay and t

RFS

timing for the device.

5) The host shall resume an Ultra DMA burst by asserting HDMARDY-.

5.5.3.4 Terminating an Ultra DMA data in burst

a) Device terminating an Ultra DMA data in burst

The following steps shall occur in the order they are listed unless otherwise specifically

allowed (see 5.6.3.5 and 5.6.3.2 for specific timing requirements):

1) The device shall initiate termination of an Ultra DMA burst by not generating

DSTROBE edges.

2) The device shall negate DMARQ no sooner than t

SS

after generating the last

DSTROBE edge. The device shall not assert DMARQ again until after the Ultra

DMA burst is terminated.

3) The device shall release DD (15:0) no later than t

AZ

after negating DMARQ.

4) The host shall assert STOP within t

LI

after the device has negated DMARQ. The host

shall not negate STOP again until after the Ultra DMA burst is terminated.

5) The host shall negate HDMARDY- within t

LI

after the device has negated DMARQ.

The host shall continue to negate HDMARDY- until the Ultra DMA burst is

terminated. Steps (4) and (5) may occur at the same time.

6) The host shall drive DD (15:0) no sooner than t

ZAH

after the device has negated

DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC

calculation (see 5.5.5):

7) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host

has asserted STOP. No data shall be transferred during this assertion. The host shall

ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra

DMA burst is terminated.

8) If the host has not placed the result of its CRC calculation on DD (15:0) since first

driving DD (15:0) during (6), the host shall place the result of its CRC calculation on

DD (15:0) (see 5.5.5).

9) The host shall negate DMACK- no sooner than t

MLI

after the device has asserted

DSTROBE and negated DMARQ and the host has asserted STOP and negated

HDMARDY-, and no sooner than t

DVS

after the host places the result of its CRC

calculation on DD (15:0).

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