CS81 Series Standard Cell
predicts performance in advance. Fujitsu supports co-sim-
ulation, emulation and high-level floor-planning to opti-
mize the power, timing, and size of the design. This
enables the designer to make effective architectural-level
decisions to achieve optimal design solutions.
Fujitsu’s design methodology supports cycle-based simula-
tors and formal verification, as well as static timing analy-
sis and the more conventional VHDL and Verilog simula-
tors. Fujitsu’s design-for-test strategy includes boundary
scan (JTAG) and full and partial scan, as well as a built-in
self-test for memory.
Applications
CS81 offers high-density standard cells for very low-power
applications. Also provided in CS81 are high-performance
and area-optimized memories, mixed-signal blocks, ana-
log functions, a rich set of IP Cores and Mega Macros,
and various I/O interfaces. The CS81 ASIC design kit,
combined with its supported EDA tool sets, is poised for
chip developments that require ease-of-tool use, proven
design flow and a quick time to market.
Mixed-Signal Macros
• A/D Converters
- 8-bit: 50 MS/s high-speed 3.3V
- 8-bit: 25 MS/s high-speed 3.3V
- 8-bit: 1 MS/s 3.3V
• D/A Converters
- 10-bit: 30 MS/s 3.3V
- 8-bit: 50 MS/s 3.3V
- 8-bit: 1 MS/s 3.3V
Multiplier Compiler
• Multiplicand (m): 4 ≤ m ≤ 32
• Multiplier (n): 4 ≤ n ≤ 32 (even numbers only)
Memory Macros
• SRAM Compiler: single and dual port (1RW/1R),
up to 72K bits per block
• High-speed SRAMs, up to 144K bits
• High-density SRAMs (1 RW)
512K ~ 1.1M bits (under development)
• Register files: 2R/2W
• ROM Compiler: up to 512K bits per block
Phase-Locked Loops
• Analog: up to 800 MHz
I/Os
• 1.8V, 2.5V, and 3.3V CMOS (2.5V is under
development)
• Slew-rate controlled
• Capable of driving large loads: 2, 4, 8, and 12 mA
sinking current
• Transceivers under development: P-CML, LVDS, PCI,
SSTL, and GTL
• AGP 2X and 4X
• 2.5 Gbps with clock recovery and
Serdes (under development)
• To be developed: 5V tolerant buffers
SOC IP Cores
• ARC 32-bit RISC
• 10/100 MAC
• 64/256 QAM
• MPEG2 Decoder/Demultiplexer
• 8VSB TV Demodulator
• AC3 Dolby Voice Decoder
• JPEG Encoder and Decoder
• PCI – 33/66 MHz, 32/64 bit cores
• USB Host Controller/Device
• I
2
C
• IDE (ATA3) Host Controller
• Smart Card I/F
• IRDA I/R Interface
• To be developed:
- ARM 7TDMI Hard Macro
- Oak DSP Hard Macro
- More IPs are being added
ASIC Design Kit and EDA Support
Verilog Logic Simulators Verilog-XL, NC Verilog,
from Cadence, Synopsys, VCS, Model-sim (Verilog)
and Mentor
VHDL/VITAL Logic VSS, Model-sim (VHDL)
Simulators from Synopsys, V-System, Leapfrog
Cadence, and Mentor
Synthesis, DFT, and STA Design Compiler, Test
tools from Synopsys Compiler, and PrimeTime
Other EDA Tools Chrysalis Design Verifyer
and Cadence DP
Fujitsu Microelectronics, Inc.
(2 pages)
(12 pages)
(216 pages)
(68 pages)
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