Fujitsu MHR2030AT User Manual Page 1

C141-E145-02ENMHR2040AT, MHR2030AT,MHR2020AT, MHR2010ATDISK DRIVESPRODUCT MANUAL

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Interface5-26 C141-E145-02EN(6) WRITE MULTIPLE (X’C5’)This command is similar to the WRITE SECTOR(S) command. The device doesnot generate interrupts (

5.3 Host CommandsC141-E145-02EN 5-27At command issuance (I/O registers setting contents)1F7H(CM)110001011F6H(DH) x L x DV Start head No. / LBA[MSB]1F

Interface5-28 C141-E145-02ENA host system can select the following transfer mode using the SET FEATUREScommand.• Multiword DMA transfer mode 0 to 2• U

5.3 Host CommandsC141-E145-02EN 5-29At command issuance (I/O registers setting contents)1F7H(CM)001111001F6H(DH) x L x DV Start head No. / LBA[MSB]1F

Interface5-30 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)0001xxxx1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

5.3 Host CommandsC141-E145-02EN 5-31At command issuance (I/O registers setting contents)1F7H(CM)0111xxxx1F6H(DH) x L x DV Head No. / LBA [MSB]1F5H(CH

Interface5-32 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)100100011F6H(DH) x x x DV Max. head No.1F5H(CH)1F4H(CL)1F3H(SN

5.3 Host CommandsC141-E145-02EN 5-33(13) IDENTIFY DEVICE DMA (X’EE’)When this command is not used to transfer data to the host in DMA mode, thiscomm

Interface5-34 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)111011001F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

5.3 Host CommandsC141-E145-02EN 5-35Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3)Word Value Description27-46 Set by a device M

C141-E145-02EN viiManual OrganizationMHR2040AT, MHR2030AT,MHR2020AT, MHR2010ATDISK DRIVESPRODUCT MANUAL(C141-E145)<This manual>• Device Overvie

Interface5-36 C141-E145-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3)Word Value Description86 *14 Valid of command sets/fun

5.3 Host CommandsC141-E145-02EN 5-37*19 Status of the Word 2 Identify information is shown as follows:37C8h The device requires the SET FEATURES sub-

Interface5-38 C141-E145-02ENBit 2: 1 = Enable the word 88Bit 1: 1 = Enable the word 64-70Bit 0: 1 = Enable the word 54-58*6 Word 59: Transfer sector c

5.3 Host CommandsC141-E145-02EN 5-39Bit 1-0: Undefined*10 WORD 82Bit 15: UndefinedBit 14: '1' = Supports the NOP command.Bit 13: '1&ap

Interface5-40 C141-E145-02ENBit 4: '1' = Supports the Removable Media Status Notification feature set.Bit 3: '1' = Supports

5.3 Host CommandsC141-E145-02EN 5-41Bit 0: '1' = From the SMART ENABLE OPERATION command*14 WORD 86Bits 15: ReservedBit 13-10: Same definit

Interface5-42 C141-E145-02ENBit 0: '1' = Supports the Mode 0*21 WORD 89MHR2040AT = X'14': 40 minutesMHR2020AT = X'0A':

5.3 Host CommandsC141-E145-02EN 5-43Bit 0: '1'= (In the case of device 0)*18 WORD 128Bit 15-9: ReservedBit 8: Security level. 0: High, 1:

Interface5-44 C141-E145-02ENTable 5.5 Features register values and settable modesFeaturesRegisterDrive operation modeX’02’ Enables the write cache fun

5.3 Host CommandsC141-E145-02EN 5-45At command issuance (I/O registers setting contents)1F7H(CM)111011111F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

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Interface5-46 C141-E145-02ENMultiword DMA transfer mode X 00100 000 (X’20’: Mode 0)00100 001 (X’21’: Mode 1)00100 010 (X’22’: Mode 2)Ultra DMA t

5.3 Host CommandsC141-E145-02EN 5-47AAM Level Sector Count registerStandard SeekSlow SeekReservedC0h-FEh, 00h80h-BFh01h-7Fh, FFhStandard Seek : Maxi

Interface5-48 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)110001101F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

5.3 Host CommandsC141-E145-02EN 5-49• SET MAX ADDRESSA successful READ NATIVE MAX ADDRESS command shall immediatelyprecede a SET MAX ADDRESS command

Interface5-50 C141-E145-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV Max head/LBA [MSB]1F

5.3 Host CommandsC141-E145-02EN 5-51At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)1F5H(CH)1F4H(CL)1F3H(

Interface5-52 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)111110011F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)xxxxxx1F2H

5.3 Host CommandsC141-E145-02EN 5-53At command issuance (I/O registers setting contents)1F7H(CM)111110011F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)x

Interface5-54 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)111110011F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)xxxxxx1F2H

5.3 Host CommandsC141-E145-02EN 5-55At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV Max head/LB

C141-E145-02EN ixContentsCHAPTER 1 Device Overview ... 1-11.1 Features 1-21.1.

Interface5-56 C141-E145-02ENTable 5.6 Diagnostic codeCode Result of diagnosticX’01’X’03’X’05’X’8x’No error detected.Data buffer compare errorROM sum c

5.3 Host CommandsC141-E145-02EN 5-57(19) READ LONG (X’22’ or X’23’)This command operates similarly to the READ SECTOR(S) command except thatthe devi

Interface5-58 C141-E145-02EN(20) WRITE LONG (X’32’ or X’33’)This command operates similarly to the READ SECTOR(S) command except thatthe device writ

5.3 Host CommandsC141-E145-02EN 5-59(21) READ BUFFER (X’E4’)The host system can read the current contents of the data buffer of the device byissuing

Interface5-60 C141-E145-02EN(22) WRITE BUFFER (X’E8’)The host system can overwrite the contents of the data buffer of the device with adesired data p

5.3 Host CommandsC141-E145-02EN 5-61(23) IDLE (X’97’ or X’E3’)Upon receipt of this command, the device sets the BSY bit of the Status register,and e

Interface5-62 C141-E145-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F

5.3 Host CommandsC141-E145-02EN 5-63(25) STANDBY (X’96’ or X’E2’)Upon receipt of this command, the device sets the BSY bit of the Status registerand

Interface5-64 C141-E145-02EN(26) STANDBY IMMEDIATE (X’94’ or X’E0’)Upon receipt of this command, the device sets the BSY bit of the Status registeran

5.3 Host CommandsC141-E145-02EN 5-65(27) SLEEP (X’99’ or X’E6’)This command is the only way to make the device enter the sleep mode.Upon receipt of

Contentsx C141-E145-02ENCHAPTER 3 Installation Conditions...3-13.1 Dimensions 3-23.2 Mo

Interface5-66 C141-E145-02EN(28) CHECK POWER MODE (X’98’ or X’E5’)The host checks the power mode of the device with this command.The host system can

5.3 Host CommandsC141-E145-02EN 5-67(29) SMART (X’B0)This command predicts the occurrence of device failures depending on thesubcommand specified in

Interface5-68 C141-E145-02ENTable 5.7 Features Register values (subcommands) and functions (1 of 3)Features Resister FunctionX’D0’ SMART Read Attribut

5.3 Host CommandsC141-E145-02EN 5-69Table 5.7 Features Register values (subcommands) and functions (2 of 3)Features Resister FunctionX’D5’ SMART Read

Interface5-70 C141-E145-02ENTable 5.7 Features Register values (subcommands) and functions (3 of 3)Features Resister FunctionX’DA’ SMART Return Status

5.3 Host CommandsC141-E145-02EN 5-71At command completion (I-O registers setting contents)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H

Interface5-72 C141-E145-02ENTable 5.8 Format of device attribute value dataByte Item0001Data format version number02 Attribute 1 Attribute ID0304Statu

5.3 Host CommandsC141-E145-02EN 5-73• Data format version numberThe data format version number indicates the version number of the dataformat of the

Interface5-74 C141-E145-02EN• Status FlagBit Meaning0 If this bit is 1, it indicates normal operations are assured with theattribute when the attribut

5.3 Host CommandsC141-E145-02EN 5-75Status Byte Meaning00h or 80h Off-line data acquisition is not executed.02h or 82h Off-line data acquisition has

ContentsC141-E145-02EN xi4.6.1 Read/write preamplifier (HDIC) 4-104.6.2 Write circuit 4-104.6.3 Read circuit 4-124.6.4 Digital PLL circuit

Interface5-76 C141-E145-02EN• Off-line data collection capabilityIndicates the method of off-line data collection carried out by the drive. Ifthe off

5.3 Host CommandsC141-E145-02EN 5-77• Insurance failure thresholdThe limit of a varying attribute value. The host compares the attribute valueswith

Interface5-78 C141-E145-02ENTable 5.11 Data format of SMART Summary Error Log (1/2)Byte Item00 Version of this function01 Pointer for the latest &qu

5.3 Host CommandsC141-E145-02EN 5-79• Command data structureIndicates the command received when an error occurs.• Error data structureIndicates the s

Interface5-80 C141-E145-02EN• SMART Self TestThe host computer can issue the SMART Execute Off-line Immediate sub-command (FR Register = D4h) and caus

5.3 Host CommandsC141-E145-02EN 5-81(30) SECURITY DISABLE PASSWORD (F6h)This command invalidates the user password already set and releases the lock

Interface5-82 C141-E145-02ENTable 5.13 Contents of security passwordWord Contents0 Control wordBit 0: Identifier0 = Compares the user passwords.1 = C

5.3 Host CommandsC141-E145-02EN 5-83(31) SECURITY ERASE PREPARE (F3h)The SECURITY ERASE UNIT command feature is enabled by issuing theSECURITY ERASE

Interface5-84 C141-E145-02ENAlthough this command invalidates the user password, the master password isretained. To recover the master password, issu

5.3 Host CommandsC141-E145-02EN 5-85• SECURITY ERASE UNITFROZEN MODE is canceled when the power is turned off, or when hardware isreseted. If this c

Contentsxii C141-E145-02EN5.5.3 Ultra DMA data in commands 5-1165.5.3.1 Initiating an Ultra DMA data in burst 5-1165.5.3.2 The data in transfe

Interface5-86 C141-E145-02ENAt command completion (I-O register contents)1F7h(ST) Status information1F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(S

5.3 Host CommandsC141-E145-02EN 5-87Table 5.15 Relationship between combination of Identifier and Security level, andoperation of the lock functionId

Interface5-88 C141-E145-02EN(35) SECURITY UNLOCKThis command cancels LOCKED MODE.The host transfers the 512-byte data shown in Table 5.12 to the devi

5.3 Host CommandsC141-E145-02EN 5-89At command completion (I-O register contents)1F7h(ST) Status information1F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(

Interface5-90 C141-E145-02ENAt command completion (I-O register contents to be read)1F7h(ST) Status information1F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3

5.3 Host CommandsC141-E145-02EN 5-91At command completion (I-O register contents)1F7h(ST) Status information1F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(

Interface5-92 C141-E145-02EN• DEVICE CONFIGURATION IDENTIFY (FR=C2h)The DEVICE CONFIGURATION IDENTIFY command returns a 512 bytedata structure is show

5.3 Host CommandsC141-E145-02EN 5-93Table 5.16 DEVICE CONFIGURATION IDENTIFY data structureWord Value Content0 X'0001' Data structure revi

Interface5-94 C141-E145-02EN(38) READ NATIVE MAX ADDRESS EXT (27H)• DescriptionThis command is used to assign the highest address that the device ca

5.3 Host CommandsC141-E145-02EN 5-95(39) SET MAX ADDRESS EXT (37H)• DescriptionThis command limits specifications so that the highest address that

ContentsC141-E145-02EN xiii6.1.4 Response to diagnostic command 6-66.2 Power Save 6-76.2.1 Power save mode 6-76.2.2 Power commands 6-9

Interface5-96 C141-E145-02ENAt command completion (I/O registers contents to be read)1F7h(ST) Status information1F6h(DH) 1 L 1 DV xx1F5h(CH) 11F5h(CH)

5.3 Host CommandsC141-E145-02EN 5-97At command issuance (I/O registers setting contents)1F7h(CM) 111010101F6h(DH) 1 L 1 DV xx1F5h(CH) P1F5h(CH) C1F4h

Interface5-98 C141-E145-02EN(41) WRITE DMA EXT (35H)• DescriptionThis command is the extended command of the WRITE DMA command.The LBA specification

5.3 Host CommandsC141-E145-02EN 5-99(42) READ DMA EXT (25H)• DescriptionThis command is the extended command of the READ DMA command. TheLBA speci

Interface5-100 C141-E145-02EN(43) WRITE MULTIPLE EXT (39H)• DescriptionThis command is the extended command of the WRITE MULTIPLEcommand. The LBA s

5.3 Host CommandsC141-E145-02EN 5-101(44) READ MULTIPLE EXT (29H)• DescriptionThis command is the extended command of the READ MULTIPLEcommand. Th

Interface5-102 C141-E145-02EN(45) WRITE SECTOR (S) EXT (34H)• DescriptionThis command is the extended command of the WRITE SECTOR (S)command. The L

5.3 Host CommandsC141-E145-02EN 5-103(46) READ SECTOR (S) EXT (24H)• DescriptionThis command is the extended command of the READ SECTOR (S)command.

Interface5-104 C141-E145-02EN5.3.3 Error postingTable 5.15 lists the defined errors that are valid for each command.Table 5.17 Command code and parame

5.3 Host CommandsC141-E145-02EN 5-105Table 5.17 Command code and parameters (2 of 2)Command name Error register (X’1F1’) Status register (X’1F7’)ICRC

Contentsxiv C141-E145-02ENIllustrationsFiguresFigure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7Figure 2.1 Disk drive outerv

Interface5-106 C141-E145-02EN5.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0prior to issue a co

5.4 Command ProtocolC141-E145-02EN 5-107words, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the

Interface5-108 C141-E145-02ENdevice to starting of the sector data transfer. Note that the host doesnot need to read the Status register for the read

5.4 Command ProtocolC141-E145-02EN 5-109The execution of these commands includes the transfer one or more sectors ofdata from the host to the device.

Interface5-110 C141-E145-02ENFigure 5.5 WRITE SECTOR(S) command protocolIMPORTANTFor transfer of a sector of data, the host needs to read Status regis

5.4 Command ProtocolC141-E145-02EN 5-111• SEEK• READY VERIFY SECTOR(S)• EXECUTE DEVICE DIAGNOSTIC• INITIALIZE DEVICE PARAMETERS• SET FEATURES• SET MU

Interface5-112 C141-E145-02EN5.4.4 Other commands• READ MULTIPLE (EXT)• SLEEP• WRITE MULTIPLE (EXT)See the description of each command.5.4.5 DMA data

5.4 Command ProtocolC141-E145-02EN 5-113The interrupt processing for the DMA transfer differs the following point.• The interrupt processing for the

Interface5-114 C141-E145-02ENgdffdeFigure 5.7 Normal DMA data transfer

5.5 Ultra DMA Feature SetC141-E145-02EN 5-1155.5 Ultra DMA Feature Set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and

ContentsC141-E145-02EN xvFigure 5.1 Interface signals 5-2Figure 5.2 Execution example of READ MULTIPLE command 5-21Figure 5.3 Read Sector(s) c

Interface5-116 C141-E145-02ENdevice compares its CRC data to the data sent from the host. If the two values donot match the device reports an error i

5.5 Ultra DMA Feature SetC141-E145-02EN 5-1178) The device may assert DSTROBE tZIORDY after the host has asserted DMACK-.Once the device has driven D

Interface5-118 C141-E145-02ENNOTE - The host shall not immediately assert STOP to initiate UltraDMA burst termination when the device stops generating

5.5 Ultra DMA Feature SetC141-E145-02EN 5-1196) The host shall drive DD (15:0) no sooner than tZAH after the device hasnegated DMARQ. For this step,

Interface5-120 C141-E145-02ENafter the device has generated a DSTROBE edge, then the host shall beprepared to receive zero, one or two additional data

5.5 Ultra DMA Feature SetC141-E145-02EN 5-1215.5.4 Ultra DMA data out commands5.5.4.1 Initiating an Ultra DMA data out burstThe following steps shall

Interface5-122 C141-E145-02ENMode. The host shall not generate two rising or falling HSTROBE edgesmore frequently than 2 tCYC for the selected Ultra

5.5 Ultra DMA Feature SetC141-E145-02EN 5-1235.5.4.4 Terminating an Ultra DMA data out bursta) Host terminating an Ultra DMA data out burstThe follow

Interface5-124 C141-E145-02ENb) Device terminating an Ultra DMA data out burstThe following steps shall occur in the order they are listed unless othe

5.5 Ultra DMA Feature SetC141-E145-02EN 5-12513) The host shall neither negate STOP nor HSTROBE until at least tACK afternegating DMACK-.14) The host

FOR SAFE OPERATIONHandling of This ManualThis manual contains important information for using this product. Read thoroughly before usingthe product.

Contentsxvi C141-E145-02ENTablesTable 1.1 Specifications 1-4Table 1.2 Model names and product numbers 1-5Table 1.3 Current and power dissipati

Interface5-126 C141-E145-02ENi) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.Note: Since no bit clock is available, the recommended

5.6 TimingC141-E145-02EN 5-1275.6 Timing5.6.1 PIO data transferFigure 5.9 shows of the data transfer timing between the device and the hostsystem.t6t

Interface5-128 C141-E145-02EN5.6.2 Multiword data transferFigure 5.10 shows the multiword DMA data transfer timing between the deviceand the host syst

5.6 TimingC141-E145-02EN 5-1295.6.3 Ultra DMA data transferFigures 5.11 through 5.20 define the timings associated with all phases of UltraDMA bursts

Interface5-130 C141-E145-02EN5.6.3.2 Ultra DMA data burst timing requirementsTable 5.18 Ultra DMA data burst timing requirements (1 of 2)NAME MODE 0(

5.6 TimingC141-E145-02EN 5-131Table 5.18 Ultra DMA data burst timing requirements (2 of 2)MODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE 4

Interface5-132 C141-E145-02ENTable 5.19 Ultra DMA sender and recipient timing requirementsMODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE 4(

5.6 TimingC141-E145-02EN 5-1335.6.3.3 Sustained Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.No

Interface5-134 C141-E145-02EN5.6.3.4 Host pausing an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Mode

5.6 TimingC141-E145-02EN 5-1355.6.3.5 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra

C141-E145-02EN 1-1CHAPTER 1 Device Overview1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic Noi

Interface5-136 C141-E145-02EN5.6.3.6 Host terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA

5.6 TimingC141-E145-02EN 5-1375.6.3.7 Initiating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Mod

Interface5-138 C141-E145-02EN5.6.3.8 Sustained Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Not

5.6 TimingC141-E145-02EN 5-1395.6.3.9 Device pausing an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA

Interface5-140 C141-E145-02EN5.6.3.10 Host terminating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DM

5.6 TimingC141-E145-02EN 5-1415.6.3.11 Device terminating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultr

Interface5-142 C141-E145-02EN5.6.4 Power-on and resetFigure 5.21 shows power-on and reset (hardware and software reset) timing.(1) Only master device

C141-E145-02EN 6-1CHAPTER 6 Operations6.1 Device Response to the Reset6.2 Power Save6.3 Defect Processing6.4 Read-Ahead Cache6.5 Write Cache

Operations6-2 C141-E145-02EN6.1 Device Response to the ResetThis section describes how the PDIAG- and DASP- signals responds when thepower of the IDD

6.1 Device Response to the ResetC141-E145-02EN 6-3Max. 31 sec.Max. 400 ms.Max. 30 sec.Max. 1 ms.If presence of a slave device isconfirmed, PDIAG- is

Device Overview1-2 C141-E145-02EN1.1 Features1.1.1 Functions and performanceThe following features of the MHR Series are described.(1) CompactThe MHR

Operations6-4 C141-E145-02ENAfter the slave device receives the hardware reset, the slave device shall report itspresence and the result of the self-d

6.1 Device Response to the ResetC141-E145-02EN 6-56.1.3 Response to software resetThe master device does not check the DASP- signal for a software re

Operations6-6 C141-E145-02EN6.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave devi

6.2 Power SaveC141-E145-02EN 6-76.2 Power SaveThe host can change the power consumption state of the device by issuing apower command to the device.6

Operations6-8 C141-E145-02EN• Upon receipt of a hard reset• Upon receipt of Idle/Idle Intermediate(4) Standby modeIn this mode, the spindle motor has

6.3 Defect ProcessingC141-E145-02EN 6-96.2.2 Power commandsThe following commands are available as power commands.• IDLE• IDLE IMMEDIATE• STANDBY• ST

Operations6-10 C141-E145-02EN6.3.2 Alternating processing for defective sectorsThe following two types of technology are used for alternating processi

6.3 Defect ProcessingC141-E145-02EN 6-11Sector (physical)Cylinder 0Head 0Defec-tivesector(Not used)Alternate cylinder 0Head 0This is assigned to an u

Operations6-12 C141-E145-02EN6.4 Read-ahead CacheRead-ahead Cache is the function for automatically reading data blocks uponcompletion of the read com

6.4 Read-ahead CacheC141-E145-02EN 6-13(1) Commands that are targets of cachingThe commands that are targets of caching are as follows:• READ SECTOR(

1.1 FeaturesC141-E145-02EN 1-31.1.3 Interface(1) Connection to ATA interfaceThe MHR-series disk drives have built-in controllers compatible with the

Operations6-14 C141-E145-02EN6.4.3 Using the read segment bufferMethods of using the read segment buffer are explained for the followingsituations.6.4

6.4 Read-ahead CacheC141-E145-02EN 6-154) The following cache valid data is for the read command that is executed next:START LBA(Logical block addres

Operations6-16 C141-E145-02ENb. Sequential hitWhen the end sector address of the read command received the last time and thetop sector address of the

6.4 Read-ahead CacheC141-E145-02EN 6-176.4.3.3 Full hitIn this situation, all read requested data is stored in the data buffer. Transfer ofthe read

Operations6-18 C141-E145-02EN6.4.3.4 Partial hitIn this situation, a part of read requested data including the top sector is stored inthe data buffer.

6.5 Write CacheC141-E145-02EN 6-196.5 Write CacheWrite Cache is the function for reducing the command processing time byseparating command control to

Operations6-20 C141-E145-02EN(3) Status report in the event of an errorThe status report concerning an error occurring during writing onto media iscre

C141-E145-02EN GL-1GlossaryActuatorHead positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (

GlossaryGL-2 C141-E145-02ENMTBFMean time between failures. The MTBF is calculated by dividing the totaloperation time (total power-on time) by the nu

GlossaryC141-E145-02EN GL-3StatusThe status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The

Device Overview1-4 C141-E145-02EN1.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specifications of the disk drives (MHR Serie

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C141-E145-02EN AB-1Acronyms and AbbreviationsAABRT Aborted commandAIC Automatic idle controlAMNF Address mark not foundATA AT attachmentAWG American w

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C141-E145-02EN IN-1IndexAactive idle mode 6-7active mode 6-7alternate cylinder assignment processing6-10alternating processing,automatic 6-11for

IndexIN-2 C141-E145-02ENOoperation 6-1operation, caching 6-12operation, read-ahead 6-12Ppartial hit 6-18pausing, device Ultra DMA data out bur

C141-E145-02ENComment FormWe would appreciate your comments and suggestions regarding this manual.Manual code C141-E145-02ENManual name MHR2040AT, MHR

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MHR2040AT, MHR2030AT, MHR2020AT, MHR2010AT DISK DRIVESPRODUCT MANUALC141-E145-02ENMHR2040AT, MHR2030AT, MHR2020AT, MHR2010AT DISK DRIVESPRODUCT MANUAL

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1.3 Power RequirementsC141-E145-02EN 1-5Table 1.1 lists the formatted capacity, number of logical cylinders, numberof heads, and number of sectors of

Device Overview1-6 C141-E145-02EN(3) Current Requirements and Power DissipationTable 1.3 lists the current and power dissipation (typical).Table 1.3 C

1.4 Environmental SpecificationsC141-E145-02EN 1-7Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on(5) Power on/off sequenceThe vo

Device Overview1-8 C141-E145-02EN1.5 Acoustic NoiseTable 1.5 lists the acoustic noise specification.Table 1.5 Acoustic noise specificationItem Specifi

1.7 ReliabilityC141-E145-02EN 1-91.7 Reliability(1) Mean time between failures (MTBF)Conditions of 300,000 h Power-on time 250H/month or less 3000H/

C141-E145-02ENRevision History(1/1)Edition DateRevised section (*1)(Added/Deleted/Altered)Details01 2001-12-28 — —02 2002-01-30*1 Section(s) with aste

Device Overview1-10 C141-E145-02EN1.8 Error RateKnown defects, for which alternative blocks can be assigned, are not included inthe error rate count b

1.10 Load/Unload FunctionC141-E145-02EN 1-11Emergency Unload other than Normal Unload is performed when the power isshut down while the heads are sti

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C141-E145-02EN 2-1CHAPTER 2 Device Configuration2.1 Device Configuration2.2 System ConfigurationThis chapter describes the internal configurations of

Device Configuration2-2 C141-E145-02EN2.1 Device ConfigurationFigure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/

2.1 Device ConfigurationC141-E145-02EN 2-3MHR2040AT3120HeadHeadMHR2020AT10MHR2030AT1203Head(Either of head 0 orhead 3 is mounted.)HeadMHR2010AT10(Eit

Device Configuration2-4 C141-E145-02EN2.2 System Configuration2.2.1 ATA interfaceFigures 2.3 and 2.4 show the ATA interface system configuration. The

2.2 System ConfigurationC141-E145-02EN 2-5IMPORTANTHA (host adaptor) consists of address decoder, driver, and receiver.ATA is an abbreviation of “AT

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C141-E145-02EN 3-1CHAPTER 3 Installation Conditions3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper SettingsThis chapter gives the external d

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Installation Conditions3-2 C141-E145-02EN3.1 DimensionsFigure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw hol

3.2 MountingC141-E145-02EN 3-33.2 MountingFor information on mounting, see the "FUJITSU 2.5-INCH HDDINTEGRATION GUIDANCE(C141-E144-01EN)."(

Installation Conditions3-4 C141-E145-02EN(2) FrameThe MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG.IMPOR

3.2 MountingC141-E145-02EN 3-5IMPORTANTBecause of breather hole mounted to the HDD, do not allow this toclose during mounting.Locating of breather ho

Installation Conditions3-6 C141-E145-02EN(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to theambient t

3.2 MountingC141-E145-02EN 3-7(5) Service areaFigure 3.6 shows how the drive must be accessed (service areas) during and afterinstallation.Figure 3.6

Installation Conditions3-8 C141-E145-02EN- General notesFigure 3.7 Handling cautions- Installation(1) Please use the driver of a low impact when you

3.3 Cable ConnectionsC141-E145-02EN 3-93.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for co

Installation Conditions3-10 C141-E145-02EN3.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors.

3.4 Jumper SettingsC141-E145-02EN 3-113.3.4 Power supply connector (CN1)Figure 3.10 shows the pin assignment of the power supply connector (CN1).Figu

C141-E145-02EN iPrefaceThis manual describes the MHR Series, 2.5-inch hard disk drives. These driveshave a built-in controller that is compatible wit

Installation Conditions3-12 C141-E145-02EN3.4.2 Factory default settingFigure 3.12 shows the default setting position at the factory.Figure 3.12 Fact

3.4 Jumper SettingsC141-E145-02EN 3-133.4.4 CSEL settingFigure 3.14 shows the cable select (CSEL) setting.ShortOpenBD2AC1Note:The CSEL setting is not

Installation Conditions3-14 C141-E145-02ENFigure 3.16 Example (2) of Cable Select3.4.5 Power Up in Standby settingWhen pin C is grounded, the drive d

C141-E145-02EN 4-1CHAPTER 4 Theory of Device Operation4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on Sequence4.5 Self-calibration4.

Theory of Device Operation4-2 C141-E145-02EN4.1 OutlineThis chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of

4.2 SubassembliesC141-E145-02EN 4-3MHR2040AT3120HeadHeadMHR2020AT10MHR2030AT1203Head(Either of head 0 orhead 3 is mounted.)HeadMHR2010AT10(Either of

Theory of Device Operation4-4 C141-E145-02EN4.3 Circuit ConfigurationFigure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3

4.3 Circuit ConfigurationC141-E145-02EN 4-55.0V3.3V- 3.0VS-DRAM SVC HDIC F-ROMMCU&HDCRDC1.8V1.8-VgeneratorcircuitFigure 4.2 Power Supply Configur

Theory of Device Operation4-6 C141-E145-02ENFigure 4.3 Circuit Configuration

4.4 Power-on SequenceC141-E145-02EN 4-74.4 Power-on SequenceFigure 4.4 describes the operation sequence of the disk drive at power-on. Theoutline is

Prefaceii C141-E145-02ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alertmessage consists

Theory of Device Operation4-8 C141-E145-02ENFigure 4.4 Power-on operation sequence4.5 Self-calibrationThe disk drive occasionally performs self-calibr

4.5 Self-calibrationC141-E145-02EN 4-9The forces are compensated by adding the measured value to the specified currentvalue to the power amplifier.

Theory of Device Operation4-10 C141-E145-02EN4.5.3 Command processing during self-calibrationThis enables the host to execute the command without wait

4.6 Read/write CircuitC141-E145-02EN 4-11Figure 4.5 Read/write circuit block diagramHDICWDX/WDY

Theory of Device Operation4-12 C141-E145-02EN4.6.3 Read circuitThe head read signal from the PreAMP is regulated by the automatic gain control(AGC) ci

4.6 Read/write CircuitC141-E145-02EN 4-13(3) Flash digitizer circuitThis circuit is 10-tap sampled analog transversal filter circuit that cosine-equa

Theory of Device Operation4-14 C141-E145-02EN4.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. Theactuator mo

4.7 Servo ControlC141-E145-02EN 4-15The major internal operations are listed below.a. Spindle motor startStarts the spindle motor and accelerates it

Theory of Device Operation4-16 C141-E145-02EN(2) Servo burst capture circuitThe servo burst capture circuit reproduces signals (position signals) that

4.7 Servo ControlC141-E145-02EN 4-174.7.2 Data-surface servo formatFigure 4.8 describes the physical layout of the servo frame. The three areasindic

PrefaceC141-E145-02EN iiiAttentionPlease forward any comments you may have regarding this manual.To make this manual easier for users to understand, o

Theory of Device Operation4-18 C141-E145-02ENFigure 4.8 Physical sector servo configuration on disk surface W/R Recovery Servo Mark Gray CodeW/R Recov

4.7 Servo ControlC141-E145-02EN 4-194.7.3 Servo frame formatAs the servo information, the IDD uses the two-phase servo generated from thegray code an

Theory of Device Operation4-20 C141-E145-02EN(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2)

4.7 Servo ControlC141-E145-02EN 4-21d) If the head is stopped at the reference cylinder from there. Track followingcontrol starts.(2) Seek operation

Theory of Device Operation4-22 C141-E145-02ENd) During phase switching, the spindle motor starts rotating in low speed, andgenerates a counter electro

C141-E145-02EN 5-1CHAPTER 5 Interface5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA Feature Set5.6 Timi

Interface5-2 C141-E145-02EN5.1 Physical Interface5.1.1 Interface signalsFigure 5.1 shows the interface signals.Figure 5.1 Interface signalsDATA 0-15:

5.1 Physical InterfaceC141-E145-02EN 5-35.1.2 Signal assignment on the connectorTable 5.1 shows the signal assignment on the interface connector.Tabl

Interface5-4 C141-E145-02EN[signal] [I/O] [Description]ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28).Pins B and D Op

5.1 Physical InterfaceC141-E145-02EN 5-5[signal] [I/O] [Description]CS0- I Chip select signal decoded from the host address bus. This signalis used

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Interface5-6 C141-E145-02EN[signal] [I/O] [Description]DMARQ O This signal is used for DMA transfer between the host system andthe device. The device

5.2 Logical InterfaceC141-E145-02EN 5-75.2.1 I/O registersCommunication between the host system and the device is done through input-output (I/O) reg

Interface5-8 C141-E145-02ENDevice/Head, Cylinder High, Cylinder Low, Sector Number registersindicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, a

5.2 Logical InterfaceC141-E145-02EN 5-9- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was notfound during RECALIBRATE command e

Interface5-10 C141-E145-02EN(5) Sector Number register (X’1F3’)The contents of this register indicates the starting sector number for thesubsequent co

5.2 Logical InterfaceC141-E145-02EN 5-11(8) Device/Head register (X’1F6’)The contents of this register indicate the device and the head number.When e

Interface5-12 C141-E145-02EN- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register isaccessed. Then this bit is cleared when the comm

5.2 Logical InterfaceC141-E145-02EN 5-13- Bit 1: Always 0.- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while theprevious

Interface5-14 C141-E145-02EN(2) Device Control register (X’3F6’)The Device Control register contains device interrupt and software reset.Bit 7 Bit 6 B

5.3 Host CommandsC141-E145-02EN 5-15Table 5.3 Command code and parameters (1 of 3)Command code (Bit) Parameters usedCommand name76543210FRSCSNCYDHREA

C141-E145-02EN vImportant Alert ItemsImportant Alert MessagesThe important alert messages in this manual are as follows:A hazardous situation could re

Interface5-16 C141-E145-02ENTable 5.3 Command code and parameters (2 of 3)Command code (Bit) Parameters usedCommand name76543210FRSCSNCYDHIDLE IMMEDIA

5.3 Host CommandsC141-E145-02EN 5-17Table 5.3 Command code and parameters (3 of 3)Command code (Bit) Parameters usedCommand name76543210FRSCSNCYDHDEV

Interface5-18 C141-E145-02END*: The command is addressed to the master device, but both the master deviceand the slave device execute it.X: Do not car

5.3 Host CommandsC141-E145-02EN 5-19CM: Command register FR: Features registerDH: Device/Head register ST: Status registerCH: Cylinder High regi

Interface5-20 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)0010000R1F6H(DH) x L x DV Start head No. / LBA[MSB]1F5H(CH)1F4

5.3 Host CommandsC141-E145-02EN 5-21final partial block is transferred. The number of sectors in the partial block to betransferred is n where n = re

Interface5-22 C141-E145-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x L x DV End head No. / LBA [

5.3 Host CommandsC141-E145-02EN 5-23At command issuance (I/O registers setting contents)1F7H(CM)1100100R1F6H(DH) x L x DV Start head No. / LBA[MSB]1F

Interface5-24 C141-E145-02ENAt command issuance (I/O registers setting contents)1F7H(CM)0100000 R1F6H(DH) x L x DV Start head No. / LBA [MSB]1F5H(CH)1

5.3 Host CommandsC141-E145-02EN 5-25If an error occurs during multiple sector write operation, the write operation isterminated at the sector where t