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4.6 Read/write Circuit
C141-E145-02EN 4-13
(3) Flash digitizer circuit
This circuit is 10-tap sampled analog transversal filter circuit that cosine-
equalizes the head read signal to the Modified Extended Partial Response
(MEEPR) waveform.
(4) Viterbi detection circuit
The sample hold waveform output from the flash digitizer circuit is sent to the
Viterbi detection circuit. The Viterbi detection circuit demodulates data
according to the survivor path sequence.
(5) MEEPRM
This circuit converts the 17-bit read data into the 16-bit NRZ data.
4.6.4 Digital PLL circuit
The drive uses constant density recording to increase total capacity. This is
different from the conventional method of recording data with a fixed data
transfer rate at all data area. In the constant density recording method, data area
is divided into zones by radius and the data transfer rate is set so that the
recording density of the inner cylinder of each zone is nearly constant. The drive
divides data area into 30 zones to set the data transfer rate.
The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that
includes the Digital PLL circuit to change the data transfer rate.
- MHR2040AT, MHR2030AT 1
- MHR2020AT, MHR2010AT 1
- DISK DRIVES 1
- PRODUCT MANUAL 1
- FOR SAFE OPERATION 2
- Revision History 3
- Overview of Manual 5
- Operating Environment 6
- Conventions 6
- Attention 7
- Liability Exception 7
- Important Alert Items 9
- Manual Organization 11
- Contents 13
- Illustrations 18
- CHAPTER 1 Device Overview 21
- 1.1 Features 22
- 1.1.3 Interface 23
- 1.2 Device Specifications 24
- 1.3 Power Requirements 25
- 1.5 Acoustic Noise 28
- 1.6 Shock and Vibration 28
- 1.7 Reliability 29
- 1.8 Error Rate 30
- 1.9 Media Defects 30
- 1.10Load/Unload Function 30
- C141-E145-02EN 2-1 33
- 2.1 Device Configuration 33
- 2.2 System Configuration 33
- 3.1 Dimensions 40
- 3.2 Mounting 41
- Installation Conditions 46
- 3-8 C141-E145-02EN 46
- Figure 3.7 Handling cautions 46
- 3.3 Cable Connections 47
- 3.3.3 Device connection 48
- 3.4 Jumper Settings 49
- 3.4.2 Factory default setting 50
- 3.4.4 CSEL setting 51
- 3-14 C141-E145-02EN 52
- 4.1 Outline 54
- 4.2 Subassemblies 54
- 4.2.3 Spindle 55
- 4.2.4 Actuator 55
- 4.2.5 Air filter 55
- 4.3 Circuit Configuration 56
- 4.3 Circuit Configuration 57
- C141-E145-02EN 4-5 57
- Theory of Device Operation 58
- 4-6 C141-E145-02EN 58
- 4.4 Power-on Sequence 59
- 4.5 Self-calibration 60
- 4.6 Read/write Circuit 62
- 4.6 Read/write Circuit 63
- C141-E145-02EN 4-11 63
- 4.6.3 Read circuit 64
- 4.6.4 Digital PLL circuit 65
- 4.7 Servo Control 66
- 4.7.3 Servo frame format 71
- 4.7.4 Actuator motor control 72
- 4.7.5 Spindle motor control 73
- CHAPTER 5 Interface 75
- 5.1 Physical Interface 76
- 5.2 Logical Interface 80
- 5.2.1 I/O registers 81
- 5.2.2 Command block registers 82
- 5.2.3 Control block registers 87
- 5.3 Host Commands 88
- 5.3.2 Command descriptions 92
- Password information 125
- (CM) 11110100 133
- 5.3.3 Error posting 178
- 5.3 Host Commands 179
- C141-E145-02EN 5-105 179
- 5.4 Command Protocol 180
- IMPORTANT 181
- 5.4.4 Other commands 186
- Interface 188
- 5-114 C141-E145-02EN 188
- 5.5 Ultra DMA Feature Set 189
- 5.5.2 Phases of operation 190
- 5.5.5 Ultra DMA CRC rules 199
- 5.6 Timing 201
- 5.6.2 Multiword data transfer 202
- 5.6.3 Ultra DMA data transfer 203
- (host) 215
- DA0, DA1, DA2 215
- CS0-, CS1 215
- 5.6.4 Power-on and reset 216
- CHAPTER 6 Operations 217
- 6.1.1 Response to power-on 218
- 6.2 Power Save 223
- 6.3 Defect Processing 225
- Sector (physical) 226
- Cylinder 0 226
- (Not used) 226
- 6.4 Read-ahead Cache 228
- 6.5 Write Cache 235
- Glossary 237
- Acronyms and Abbreviations 241
- Comment Form 245
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