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Interface
5-116 C141-E145-02EN
device compares its CRC data to the data sent from the host. If the two values do
not match the device reports an error in the error register at the end of the
command. If an error occurs during one or more Ultra DMA bursts for any one
command, at the end of the command, the device shall report the first error that
occurred.
5.5.2 Phases of operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data
in or data out bursts. Each Ultra DMA burst has three mandatory phases of
operation: the initiation phase, the data transfer phase, and the Ultra DMA burst
termination phase. In addition, an Ultra DMA burst may be paused during the
data transfer phase (see 5.5.3 and 5.5.4 for the detailed protocol descriptions for
each of these phases, 5.6 defines the specific timing requirements). In the
following rules DMARDY- is used in cases that could apply to either
DDMARDY- or HDMARDY-, and STROBE is used in cases that could apply to
either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
a) An Ultra DMA burst is defined as the period from an assertion of DMACK-
by the host to the subsequent negation of DMACK-.
b) A recipient shall be prepared to receive at least two data words whenever it
enters or resumes an Ultra DMA burst.
5.5.3 Ultra DMA data in commands
5.5.3.1 Initiating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.1 and 5.6.3.2 for specific timing requirements):
1) The host shall keep DMACK- in the negated state before an Ultra DMA burst
is initiated.
2) The device shall assert DMARQ to initiate an Ultra DMA burst. After
assertion of DMARQ the device shall not negate DMARQ until after the first
negation of DSTROBE.
3) Steps (3), (4) and (5) may occur in any order or at the same time. The host
shall assert STOP.
4) The host shall negate HDMARDY-.
5) The host shall negate CS0-, CS1-, DA2, DA1, and DA0. The host shall keep
CS0-, CS1-, DA2, DA1, and DA0 negated until after negating DMACK- at
the end of the burst.
6) Steps (3), (4) and (5) shall have occurred at least t
ACK
before the host asserts
DMACK-. The host shall keep DMACK- asserted until the end of an Ultra
DMA burst.
7) The host shall release DD (15:0) within t
AZ
after asserting DMACK-.
- MHR2040AT, MHR2030AT 1
- MHR2020AT, MHR2010AT 1
- DISK DRIVES 1
- PRODUCT MANUAL 1
- FOR SAFE OPERATION 2
- Revision History 3
- Overview of Manual 5
- Operating Environment 6
- Conventions 6
- Attention 7
- Liability Exception 7
- Important Alert Items 9
- Manual Organization 11
- Contents 13
- Illustrations 18
- CHAPTER 1 Device Overview 21
- 1.1 Features 22
- 1.1.3 Interface 23
- 1.2 Device Specifications 24
- 1.3 Power Requirements 25
- 1.5 Acoustic Noise 28
- 1.6 Shock and Vibration 28
- 1.7 Reliability 29
- 1.8 Error Rate 30
- 1.9 Media Defects 30
- 1.10Load/Unload Function 30
- C141-E145-02EN 2-1 33
- 2.1 Device Configuration 33
- 2.2 System Configuration 33
- 3.1 Dimensions 40
- 3.2 Mounting 41
- Installation Conditions 46
- 3-8 C141-E145-02EN 46
- Figure 3.7 Handling cautions 46
- 3.3 Cable Connections 47
- 3.3.3 Device connection 48
- 3.4 Jumper Settings 49
- 3.4.2 Factory default setting 50
- 3.4.4 CSEL setting 51
- 3-14 C141-E145-02EN 52
- 4.1 Outline 54
- 4.2 Subassemblies 54
- 4.2.3 Spindle 55
- 4.2.4 Actuator 55
- 4.2.5 Air filter 55
- 4.3 Circuit Configuration 56
- 4.3 Circuit Configuration 57
- C141-E145-02EN 4-5 57
- Theory of Device Operation 58
- 4-6 C141-E145-02EN 58
- 4.4 Power-on Sequence 59
- 4.5 Self-calibration 60
- 4.6 Read/write Circuit 62
- 4.6 Read/write Circuit 63
- C141-E145-02EN 4-11 63
- 4.6.3 Read circuit 64
- 4.6.4 Digital PLL circuit 65
- 4.7 Servo Control 66
- 4.7.3 Servo frame format 71
- 4.7.4 Actuator motor control 72
- 4.7.5 Spindle motor control 73
- CHAPTER 5 Interface 75
- 5.1 Physical Interface 76
- 5.2 Logical Interface 80
- 5.2.1 I/O registers 81
- 5.2.2 Command block registers 82
- 5.2.3 Control block registers 87
- 5.3 Host Commands 88
- 5.3.2 Command descriptions 92
- Password information 125
- (CM) 11110100 133
- 5.3.3 Error posting 178
- 5.3 Host Commands 179
- C141-E145-02EN 5-105 179
- 5.4 Command Protocol 180
- IMPORTANT 181
- 5.4.4 Other commands 186
- Interface 188
- 5-114 C141-E145-02EN 188
- 5.5 Ultra DMA Feature Set 189
- 5.5.2 Phases of operation 190
- 5.5.5 Ultra DMA CRC rules 199
- 5.6 Timing 201
- 5.6.2 Multiword data transfer 202
- 5.6.3 Ultra DMA data transfer 203
- (host) 215
- DA0, DA1, DA2 215
- CS0-, CS1 215
- 5.6.4 Power-on and reset 216
- CHAPTER 6 Operations 217
- 6.1.1 Response to power-on 218
- 6.2 Power Save 223
- 6.3 Defect Processing 225
- Sector (physical) 226
- Cylinder 0 226
- (Not used) 226
- 6.4 Read-ahead Cache 228
- 6.5 Write Cache 235
- Glossary 237
- Acronyms and Abbreviations 241
- Comment Form 245
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