Fujitsu MPG3XXXAH-E User Manual

C141-E116-01ENMPG3xxxAH-EDISK DRIVESPRODUCT MANUAL

C141-E116-01EN ixCONTENTSpageCHAPTER 1 DEVICE OVERVIEW...1 - 11

C141-E116-01EN 5 - 33Table 5.5 Information to be read by IDENTIFY DEVICE command (5 of 6)Bit 4: Removable Media Status Notification feature set suppor

5 - 34 C141-E116-01ENTable 5.5 Information to be read by IDENTIFY DEVICE command (6 of 6)*20 Word 89: Time required for SECURITY ERASE UNIT command to

C141-E116-01EN 5 - 35(13) IDENTIFY DEVICE DMA (X'EE')When this command is not used to transfer data to the host in DMA mode, this command fu

5 - 36 C141-E116-01ENTable 5.6 Features register values and settable modesFeatures Register Drive operation modeX‘02’ Enables the write cache function

C141-E116-01EN 5 - 37At command issuance (I/O registers setting contents)1F7H(CM) 111011111F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

5 - 38 C141-E116-01ENSubcommand code 42h allows the host to enable the Automatic Acoustic Management feature set.To enable the Automatic Acoustic Mana

C141-E116-01EN 5 - 39At command issuance (I/O registers setting contents)1F7H(CM) 110001101F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

5 - 40 C141-E116-01EN• Both devices shall execute self-diagnosis.• The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.•

C141-E116-01EN 5 - 41(17) FORMAT TRACK (X'50')Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte

5 - 42 C141-E116-01EN• The command is issued in a sequence of the READ LONG or WRITE LONG (to the sameaddress) command issuance. (WRITE LONG command

C141-E116-01ENx3.4.2 Cable connector specifications...3 - 9

C141-E116-01EN 5 - 43At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(

5 - 44 C141-E116-01EN(22) IDLE (X'97' or X'E3')Upon receipt of this command, the device sets the BSY bit of the Status register, a

C141-E116-01EN 5 - 45At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(

5 - 46 C141-E116-01EN(24) STANDBY (X'96' or X'E2')Upon receipt of this command, the device sets the BSY bit of the Status register

C141-E116-01EN 5 - 47At command issuance (I/O registers setting contents)1F7H(CM) X'94' or X'E0'1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F

5 - 48 C141-E116-01ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(

C141-E116-01EN 5 - 49At command issuance (I/O registers setting contents)1F7H(CM) X'98' or X'E5'1F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F

5 - 50 C141-E116-01ENTable 5.8 Features Register values (subcommands) and functions (1/2)Features Resister FunctionX’D0’ SMART Read Attribute Values:

C141-E116-01EN 5 - 51Table 5.8 Features Register values (subcommands) and functions (2/2)X’D5’ SMART Read Logging Data:This subcommand is used to tra

5 - 52 C141-E116-01ENThe host must regularly issue the SMART Read Attribute Values subcommand (FR register =D0h), SMART Save Attribute Values subcomma

C141-E116-01EN xiCHAPTER 5 INTERFACE...5 - 15.1

C141-E116-01EN 5 - 53Table 5.9 Device attribute data structureByte (Hex) Description0001Data structure revision number *102Attribute ID number *20304

5 - 54 C141-E116-01ENTable 5.10 Warranty failure threshold data structureByte (Hex) Description0001Data structure revision number *102Attribute ID nu

C141-E116-01EN 5 - 55*2 Attribute IDThe attribute ID is defined as follows:Attribute ID (Dec) Description0 (Indicates unused attribute data)1 Read err

5 - 56 C141-E116-01EN*3 Status flagBit Description0 If this bit is set to 1, it indicates the attribute is guaranteed fornormal operation when an attr

C141-E116-01EN 5 - 57*7 Off-line data collection statusValues Description00h or 80h Off-line data collection is not started.01h or 81h Reserved02h or

5 - 58 C141-E116-01EN*9 Off-line data collection capability [16Fh]Bit Description0 If this bit is set to 1, it indicates SMART EXECUTE OFF-LINEIMMEDIA

C141-E116-01EN 5 - 59*15 Attribute thresholdThe limit of a varying attribute value. The host compares the attribute values with thethresholds to iden

5 - 60 C141-E116-01ENTable 5.12 Error logging data structureAddress(Hex)Description00 SMART error logging version 01h01 Index pointer of latest error

C141-E116-01EN 5 - 61Table 5.13 Self Test log data structureByte Description0 to 1 Data Structure Revision Number = 0x00011st Descriptor Entry2 Self

5 - 62 C141-E116-01EN(29) FLUSH CACHE (X ‘E7’)This command is use by the host to request the device to flush the write cache. If the write cacheis to

C141-E116-01ENxii5.6.3 Ultra DMA data transfer...

C141-E116-01EN 5 - 63(30) SECURITY DISABLE PASSWORD (F6h)This command invalidates the user password already set and releases the lock function.The hos

5 - 64 C141-E116-01ENAt command issuance (I-O registers setting contents)1F7H(CM) 111101101F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

C141-E116-01EN 5 - 65At command issuance (I-O registers setting contents)1F7H(CM) 111100111F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

5 - 66 C141-E116-01ENAt command issuance (I-O registers setting contents)1F7H(CM) 111101001F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

C141-E116-01EN 5 - 67• READ DMA • WRITE LONG • SECURITY DISABLE PASSWORD• READ LONG • WRITE MULTIPLE • SECURITY FREEZE LOCK• READ MULTIPLE • W

5 - 68 C141-E116-01ENTable 5.15 Contents of SECURITY SET PASSWORD dataWord Contents0 Control wordBit 0 Identifier0 = Sets a user password.1 = Sets a

C141-E116-01EN 5 - 69At command issuance (I-O registers setting contents)1F7H(CM) 111100011F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

5 - 70 C141-E116-01ENAt command issuance (I-O registers setting contents)1F7H(CM) 111100101F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

C141-E116-01EN 5 - 71At command issuance (I/O registers setting contents)1F7H(CM) 111110011F6H(DH)×L×DV Max head/LBA [MSB]1F5H(CH)1F4H(CL)1F3H(SN)Max.

5 - 72 C141-E116-01ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) 1 L 1 DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

C141-E116-01EN xiiiFIGURESpage1.1 Current fluctuation (Typ.) when power is turned on ...1 -

C141-E116-01EN 5 - 73(36-4) SET MAX UNLOCK (F9)This command requests a transfer of a single sector of data from the host.The password supplied in the

5 - 74 C141-E116-01EN• SET MAX ADDRESS• SET MAX SET PASSWORD• SET MAX LOCK• SET MAX UNLOCKAt command issuance (I/O registers setting contents)1F7H

C141-E116-01EN 5 - 75At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×××DV Max head/LBA [MSB]1F5H(CH)1F4H(

5 - 76 C141-E116-01EN5.3.3 Error postingTable 5.17 lists the defined errors that are valid for each command.Table 5.17 Command code and parametersComm

C141-E116-01EN 5 - 775.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0 prior to issue acommand. I

C141-E116-01EN5 - 78Status readStatus read*1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from

C141-E116-01EN 5 - 79Note:For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clearINTRQ (interrup

C141-E116-01EN5 - 80a) The host writes any required parameters to the Features, Sector Count, Sector Number,Cylinder, and Device/Head registers.b) The

C141-E116-01EN 5 - 81Note:For transfer of a sector of data, the host needs to read Status register (X'1F7') in order to clearINTRQ (interrup

C141-E116-01EN5 - 825.4.4 Other commands• READ MULTIPLE• SLEEP• WRITE MULTIPLESee the description of each command.5.4.5 DMA data transfer commands•

C141-E116-01ENxiv5.3 Protocol for command abort...5 - 7

C141-E116-01EN 5 - 83Status readExpandedgfec, daCommandBSYINTRQDRDY~Parameter writeDRQData transfer• •• •DRQ[Multiword DMA transfer]• • • •DMACK-DMARQ

C141-E116-01EN5 - 845.5 Ultra DMA feature set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands.When th

C141-E116-01EN 5 - 855.5.2 Phases of operationAn Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data outbursts. Eac

C141-E116-01EN5 - 8611) The device shall drive the first word of the data transfer onto DD (15:0). This step may occurwhen the device first drives DD

C141-E116-01EN 5 - 873) The device shall stop generating DSTROBE edges within tRFS of the host negatingHDMARDY-.4) If the host negates HDMARDY- within

C141-E116-01EN5 - 8810) The device shall latch the host's CRC data from DD (15:0) on the negating edge ofDMACK-.11) The device shall compare the

C141-E116-01EN 5 - 8910) If the host has not placed the result of its CRC calculation on DD (15:0) since first drivingDD (15:0) during (9), the host s

C141-E116-01EN5 - 909) The device shall assert DDMARDY- within tLI after the host has negated STOP. Afterasserting DMARQ and DDMARDY- the device shal

C141-E116-01EN 5 - 91b) Device pausing an Ultra DMA data out burst1) The device shall not pause an Ultra DMA burst until at least one data word of an

C141-E116-01EN5 - 929) The device shall compare the CRC data received from the host with the results of its ownCRC calculation. If a miscompare error

C141-E116-01EN xvTABLESpage1.1 Specifications ...

C141-E116-01EN 5 - 9311) The device shall compare the CRC data received from the host with the results of its ownCRC calculation. If a miscompare err

C141-E116-01EN5 - 94i) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.Note: Since no bit clock is available, the recommended approach

C141-E116-01EN 5 - 955.6 Timing5.6.1 PIO data transferFigure 5.8 shows of the data transfer timing between the device and the host system.t6t12t11t10t

C141-E116-01EN5 - 965.6.2 Multiword data transferFigure 5.9 shows the multiword DMA data transfer timing between the device and the host system.tFtEtH

C141-E116-01EN 5 - 975.6.3 Ultra DMA data transferFigures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.Table 5.

C141-E116-01EN5 - 985.6.3.2 Ultra DMA data burst timing requirementsTable 5.19 Ultra DMA data burst timing requirements (1 of 2)NAMEMODE 0(in ns)MODE

C141-E116-01EN 5 - 99Table 5.19 Ultra DMA data burst timing requirements (2 of 2)MODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE 4(in ns)MODE

C141-E116-01EN5 - 100Table 5.20 Ultra DMA sender and recipient timing requirementsMODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE 4(in ns)MOD

C141-E116-01EN 5 - 1015.6.3.3 Sustained Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:DD (15

C141-E116-01EN5 - 1025.6.3.4 Host pausing an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Notes:

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C141-E116-01EN 5 - 1035.6.3.5 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes

C141-E116-01EN5 - 1045.6.3.6 Host terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.No

C141-E116-01EN 5 - 1055.6.3.7 Initiating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:T

C141-E116-01EN5 - 1065.6.3.8 Sustained Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:DD (15

C141-E116-01EN 5 - 1075.6.3.9 Device pausing an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.No

C141-E116-01EN5 - 1085.6.3.10 Host terminating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

C141-E116-01EN 5 - 1095.6.3.11 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Mode

C141-E116-01EN5 - 1105.6.4 Power-on and resetFigure 5.20 shows power-on and reset (hardware and software reset) timing.(1) Only master device is prese

C141-E116-01EN 6 - 1CHAPTER 6 OPERATIONS6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cach

C141-E116-01EN6 - 26.1.1 Response to power-onAfter the master device (device 0) releases its own power-on reset state, the master device shallcheck a

C141-E116-01EN 1 - 1CHAPTER 1 DEVICE OVERVIEW1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic

C141-E116-01EN 6 - 36.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to the power-on reset.Upon re

C141-E116-01EN6 - 46.1.3 Response to software resetThe master device does not check the DASP- signal for a software reset. If a slave device ispresen

C141-E116-01EN 6 - 56.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slavedevice is pr

C141-E116-01EN6 - 66.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium, the IDD alwaysimplements the add

C141-E116-01EN 6 - 76.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, andphysica

C141-E116-01EN6 - 8(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0, physical head 0, andphysical sector 1. The

C141-E116-01EN 6 - 9(1) Active modeIn this mode, all the electric circuit in the device are active or the device is under seek, read orwrite operation

C141-E116-01EN6 - 10• CHECK POWER MODE command(4) Sleep modeThe power consumption of the drive is minimal in this mode. The drive enters only the st

C141-E116-01EN 6 - 116.4.1 Spare areaFollowing two types of spare area are provided in the user space.1) Spare sector for sector slip:used for alterna

C141-E116-01EN6 - 12(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder.This processing is p

C141-E116-01EN1 - 2(4) Average positioning timeUse of a rotary voice coil motor in the head positioning mechanism greatly increases thepositioning spe

C141-E116-01EN 6 - 136.5 Read-Ahead CacheAfter a read command which reads the data from the disk medium is completed, the read-aheadcache function rea

C141-E116-01EN6 - 146.5.2 Caching operationThe caching operation is performed only at receipt of the following commands. The device transfersdata fro

C141-E116-01EN 6 - 156.5.3 Usage of read segmentThis subsection explains the usage of the read segment buffer at following cases.(1) Miss-hit (no hit)

C141-E116-01EN6 - 16(3) Sequential readWhen the disk drive receives the read command that targets the sequential address to the previousread command,

C141-E116-01EN 6 - 17b. Sequential hitWhen the last sector address of the previous read command is sequential to the lead sectoraddress of the receive

C141-E116-01EN6 - 18(3) Full hit (hit all)All requested data are stored in the data buffer. The disk drive starts transferring the requesteddata from

C141-E116-01EN 6 - 191) The disk drive sets the HAP to the address where the partially hit data is stored, and sets theDAP to the address just after t

C141-E116-01EN6 - 206.6 Write CacheThe write cache function of the drive makes a high speed processing in the case that data to bewritten by a write c

C141-E116-01EN 6 - 21At the time that the drive has stopped the command execution after the error recovery has failed,the write cache function is disa

FUJITSU LIMITEDBusiness PlanningSolid Square East Tower580 Horikawa-cho,Saiwai-ku, Kawasaki,210-0913, JapanTEL: 81-44-540-4056FAX: 81-44-540-4123FUJIT

C141-E116-01EN iREVISION RECORDEdition Date published Revised contents01 Oct., 2000Specification No.: C141-E116-**ENThe contents of this manual is su

C141-E116-01EN 1 - 3(5) Error correction and retry by ECCIf a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes E

Reader Comment FormWe would appreciate your comments and suggestions for improving this publication.Publication No. Rev. Letter Title Current DateHow

C141-E116-01EN1 - 41.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specifications of the disk drive.Table 1.1 SpecificationsM

C141-E116-01EN 1 - 5Model Formatted Capacity No. of Cylinder No. of Heads No. of SectorsMPG3204AH-E 20,496 MB 16,383 16 63MPG3307AH-E 30,743 MB 16,383

C141-E116-01EN1 - 6(3) Current Requirements and Power DissipationTable 1.3 lists the current and power dissipation.Table 1.3 Current and power dissipa

C141-E116-01EN 1 - 7(4) Current fluctuation (Typ.) when power is turned onNote:Maximum current is 1.95A.Figure 1.1 Current fluctuation (Typ.) when pow

C141-E116-01EN1 - 81.4 Environmental SpecificationsTable 1.4 lists the environmental specifications.Table 1.4 Environmental specificationsTemperature•

C141-E116-01EN 1 - 91.6 Shock and VibrationTable 1.6 lists the shock and vibration specification.Table 1.6 Shock and vibration specificationVibration

C141-E116-01EN1 - 10(4) Service lifeIn situations where management and handling are correct, the disk drive requires no overhaul forfive years when th

C141-E116-01EN 2 - 1CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration2.2 System Configuration2.1 Device ConfigurationFigure 2.1 shows the disk d

C141-E116-01EN2 - 2(1) DiskThe outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks usedvaries with the model, as d

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C141-E116-01EN 2 - 32.2 System Configuration2.2.1 ATA interfaceFigures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pi

C141-E116-01EN2 - 4IMPORTANTHA (host adapter) consists of address decoder, driver, and receiver.ATA is an abbreviation of "AT attachment".

C141-E116-01EN 3 - 1CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions3.2 Handling Cautions3.3 Mounting3.4 Cable Connections3.5 Jumper Settings3.1 Dimen

C141-E116-01EN3 - 2Figure 3.1 Dimensions

C141-E116-01EN 3 - 33.2 Handling CautionsPlease keep the following cautions, and handle the HDD under the safety environment.3.2.1 General notesFigure

C141-E116-01EN3 - 43.3 Mounting(1) DirectionFigure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in anydirectio

C141-E116-01EN 3 - 5Figure 3.4 Limitation of side-mountingFigure 3.5 Mounting frame structure5.0 or less4.5 orless2BFrame of systemcabinetDetails of B

C141-E116-01EN3 - 6(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperatureat a point

C141-E116-01EN 3 - 7(5) Service areaFigure 3.7 shows how the drive must be accessed (service areas) during and after installation.Figure 3.7 Service a

C141-E116-01EN3 - 83.4 Cable Connections3.4.1 Device connectorThe disk drive has the connectors and terminals listed below for connecting external dev

C141-E116-01EN iiiMANUAL ORGANIZATIONMPG3xxxAH-EDISK DRIVESPRODUCTMANUAL(C141-E116)<This manual>• DEVICE OVERVIEW• DEVICE CONFIGURATION• INST

C141-E116-01EN 3 - 93.4.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors for Host system that d

C141-E116-01EN3 - 103.4.4 Power supply connector (CN1)Figure 3.10 shows the pin assignment of the power supply connector (CN1).(Viewed from cable side

C141-E116-01EN 3 - 11openConnector 2Connector 1System BoardConnectorPin 2 (Ground)Pin 19 (Ground)Pin 22 (Ground)Pin 24 (Ground)Pin 26 (Ground)Positi

C141-E116-01EN3 - 12openHost detected CBLID- below VILHost Device 0Device 1with 80-conductor cablewith 40-conductor cablePDIAG-: CBLID- conductor PDIA

C141-E116-01EN 3 - 133.5 Jumper Settings3.5.1 Location of setting jumpersFigure 3.14 shows the location of the jumpers to select drive configuration a

C141-E116-01EN3 - 143.5.2 Factory default settingFigure 3.15 shows the default setting position at the factory. (Master device setting)Figure 3.15 Fac

C141-E116-01EN 3 - 15CSEL connected to the interface cable selectioncan be done by the special interface cable.864297531Figure 3.17 Jumper setting of

C141-E116-01EN3 - 16(3) Special jumper settings(a) 2.1 GB clip (Limit capacity to 2.1 GB) / 33.8 GB clip (Limit capacity to 33.8 GB)If the drive canno

C141-E116-01EN 4 - 1CHAPTER 4 THEORY OF DEVICE OPERATION4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on sequence4.5 Self-calibratio

C141-E116-01EN4 - 24.2.2 HeadFigure 4.1 shows the read/write head structures. The Numerals 0 to 3 indicate read/write heads.These heads are raised fr

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C141-E116-01EN 4 - 34.2.4 ActuatorThe actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the headcarriage along the inn

C141-E116-01EN4 - 44.3 Circuit ConfigurationFigure 4.2 shows the disk drive circuit configuration.(1) Read/write circuitThe read/write circuit consist

C141-E116-01EN 4 - 5Figure 4.2 MPG3xxxAH Block diagramData BufferSDRAMFlash ROMFROMSVCHA13627HDC & MCU & RDCCL-SH8671 (Himalaya-2)MCUARM7TDMIR

C141-E116-01EN4 - 64.4 Power-on SequenceFigure 4.3 describes the operation sequence of the disk drive at power-on. The outline is describedbelow.a) A

C141-E116-01EN 4 - 7c)b)a)Release heads fromactuator lockConfirming spindle motorspeedSelf-diagnosis 2• Data buffer write/read testThe spindle moto

C141-E116-01EN4 - 84.5 Self-calibrationThe disk drive occasionally performs self-calibration in order to sense and calibrate mechanicalexternal forces

C141-E116-01EN 4 - 94.5.2 Execution timing of self-calibrationSelf-calibration is executed when:• The power is turned on.• The self-calibration execu

C141-E116-01EN4 - 104.6 Read/write CircuitThe read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the readcircuit,

C141-E116-01EN 4 - 114.6.3 Read circuitThe head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit.Then the output

C141-E116-01EN4 - 124.6.4 Synthesizer circuitThe drive uses constant density recording to increase total capacity. This is different from theconventi

C141-E116-01EN vPREFACEThis manual describes the MPG3xxxAH-E series, a 3.5-inch hard disk drive with a BUILT-IN controllerthat is compatible with the

C141-E116-01EN 4 - 134.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. The actuator motor iscontrolled for mo

C141-E116-01EN4 - 14b. Move head to reference cylinderDrives the VCM to position the head at the any cylinder in the data area. The logical initialcy

C141-E116-01EN 4 - 15Figure 4.5 Physical sector servo configuration on disk surface(2) Servo burst capture circuitThe four servo signals can be synchr

C141-E116-01EN4 - 16(4) D/A converter (DAC)The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by theDSP unit into

C141-E116-01EN 4 - 174.7.3 Servo frame formatAs the servo information, the drive uses the two-phase servo generated from the gray code and PosA to D.

C141-E116-01EN4 - 18(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2) Servo mark (ASM, SSM)This

C141-E116-01EN 4 - 19b) A current is fed to the VCM to move the head toward the outer circumference.c) When the servo mark is detected the head is mov

C141-E116-01EN4 - 20d) During phase switching, the spindle motor starts rotating in low speed, and generates a counterelectromotive force. The SVC de

C141-E116-01EN 5 - 1CHAPTER 5 INTERFACE5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA feature set5.6 T

C141-E116-01EN5 - 25.1 Physical Interface5.1.1 Interface signalsTable 5.1 shows the interface signals.Table 5.1 Interface signalsDescription Host Dir

vi C141-E116-01ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alert message consists of an

C141-E116-01EN 5 - 35.1.2 Signal assignment on the connectorTable 5.2 shows the signal assignment on the interface connector.Table 5.2 Signal assignme

C141-E116-01EN5 - 4[signal] [I/O] [Description]DIOR– I DIOR– is the strobe signal asserted by the host to read deviceregisters or the data port.HDMARD

C141-E116-01EN 5 - 5[signal] [I/O] [Description]IORDY O This signal is negated to extend the host transfer cycle of any host registeraccess (Read or W

C141-E116-01EN5 - 65.2 Logical InterfaceThe device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or L

C141-E116-01EN 5 - 7Table 5.3 I/O registersI/O registersRead operation Write operationCommand block registers10000Data Data X'1F0'10001Error

C141-E116-01EN5 - 85.2.2 Command block registers(1) Data register (X'1F0')The Data register is a 16-bit register for data block transfer bet

C141-E116-01EN 5 - 9[Diagnostic code]X'01': No Error Detected.X'02': HDC Register Compare ErrorX'03': Data Buffer Compar

C141-E116-01EN5 - 10(6) Cylinder Low register (X'1F4')The contents of this register indicates low-order 8 bits of the starting cylinder addr

C141-E116-01EN 5 - 11(9) Status register (X'1F7')The contents of this register indicate the status of the device. The contents of this regi

C141-E116-01EN5 - 12- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data ofword unit or byte unit between th

C141-E116-01EN viiLIABILITY EXCEPTION"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.Fujitsu is not l

C141-E116-01EN 5 - 135.2.3 Control block registers(1) Alternate Status register (X'3F6')The Alternate Status register contains the same info

C141-E116-01EN5 - 145.3.1 Command code and parametersTable 5.4 lists the supported commands, command code and the registers that needed parametersare

C141-E116-01EN 5 - 15Table 5.4 Command code and parameters (2 of 2)Command code (Bit) Parameters used76543210FRSCSNCYDHSTANDBY IMMEDIATE 1101011000100

C141-E116-01EN5 - 165.3.2 Command descriptionsThe contents of the I/O registers to be necessary for issuing a command and the example indicationof the

C141-E116-01EN 5 - 17Note:1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH,CL and SN registers indicate

C141-E116-01EN5 - 18At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)1

C141-E116-01EN 5 - 19Figure 5.1 shows an example of the execution of the READ MULTIPLE command.• Block count specified by SET MULTIPLE MODE command =

C141-E116-01EN5 - 20(3) READ DMA (X'C8' or X'C9')This command operates similarly to the READ SECTOR(S) command except for followin

C141-E116-01EN 5 - 21At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)

C141-E116-01EN5 - 22At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)1

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C141-E116-01EN 5 - 23At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)

5 - 24 C141-E116-01ENThe contents of the command block registers related to addresses after the transfer of a data blockcontaining an erred sector are

C141-E116-01EN 5 - 251) Multiword DMA transfer mode 2:Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES co

5 - 26 C141-E116-01ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)

C141-E116-01EN 5 - 27(10) SEEK (X'7x', x : X'0' to X'F')This command performs a seek operation to the track and selects

5 - 28 C141-E116-01EN(11) INITIALIZE DEVICE PARAMETERS (X'91')The host system can set the number of sectors per track and the maximum head n

C141-E116-01EN 5 - 29At command issuance (I/O registers setting contents)1F7H(CM) 111011001F6H(DH)×××DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H(FR)xxxx

5 - 30 C141-E116-01ENTable 5.5 Information to be read by IDENTIFY DEVICE command (2 of 6)Word Value Description54 (Variable) Number of current Cylinde

C141-E116-01EN 5 - 31Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 6)*1 Word 0: General configurationBit 15: 0 = ATA device 0Bit

5 - 32 C141-E116-01ENTable 5.5 Information to be read by IDENTIFY DEVICE command (4 of 6)*12 Word 63: Multiword DMA transfer modeBit 15-11: ReservedBi