Fujitsu MHL2300AT User Manual

C141-E104-02ENMHL2300AT, MHM2200AT,MHM2150AT, MHM2100ATDISK DRIVESPRODUCT MANUAL

C141-E104-02EN vImportant Alert ItemsImportant Alert MessagesThe important alert messages in this manual are as follows:CAUTIONA hazardous situation c

5.3 Host CommandsC141-E104-02EN 5-23At command issuance (I/O registers setting contents)1F7H(CM)0100000R1F6H(DH) x L x DV Start head No. /LBA[MSB]1F5

Interface5-24 C141-E104-02ENIf an error occurs during multiple sector write operation, the write operation isterminated at the sector where the error

5.3 Host CommandsC141-E104-02EN 5-25(6) WRITE MULTIPLE (X’C5’)This command is similar to the WRITE SECTOR(S) command. The device doesnot generate int

Interface5-26 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)110001011F6H(DH) x L x DV Start head No. /LBA[MSB]1F5H(CH)1F4H

5.3 Host CommandsC141-E104-02EN 5-27A host system can select the following transfer mode using the SET FEATUREScommand.• Multiword DMA transfer mode

Interface5-28 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)001111001F6H(DH) x L x DV Start head No. /LBA[MSB]1F5H(CH)1F4H

5.3 Host CommandsC141-E104-02EN 5-29At command issuance (I/O registers setting contents)1F7H(CM)0001xxxx1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

Interface5-30 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)0111xxxx1F6H(DH) x L x DV Head No. /LBA [MSB]1F5H(CH)1F4H(CL)1

5.3 Host CommandsC141-E104-02EN 5-31At command issuance (I/O registers setting contents)1F7H(CM)100100011F6H(DH) x x x DV Max. head No.1F5H(CH)1F4H(C

Interface5-32 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)111011001F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

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5.3 Host CommandsC141-E104-02EN 5-33Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 8)Word Value Description23-26 – Firmware revisi

Interface5-34 C141-E104-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (3 of 8)Word Value Description85 *12 Valid of command sets/fun

5.3 Host CommandsC141-E104-02EN 5-35Table 5.4 Information to be read by IDENTIFY DEVICE command (4 of 8)Bit 13: Standby timer value. Factory default

Interface5-36 C141-E104-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (5 of 8)Bit 1 = 1 Mode 4Bit 0 = 1 Mode 3*9 WORD 80Bit 15-6:

5.3 Host CommandsC141-E104-02EN 5-37Table 5.4 Information to be read by IDENTIFY DEVICE command (6 of 8)Bit 5: '1' = Supports the Power-Up

Interface5-38 C141-E104-02ENTable 5.4 Information to be read by IDENTIFY DEVICE command (7 of 8)Bits 2-0: Same definition as WORD 83.*14 WORD 88Bit 15

5.3 Host CommandsC141-E104-02EN 5-39Table 5.4 Information to be read by IDENTIFY DEVICE command (8 of 8)'00' = Reserved'01' = Usi

Interface5-40 C141-E104-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F

5.3 Host CommandsC141-E104-02EN 5-41Table 5.5 Features register values and settable modesFeaturesRegisterDrive operation modeX’02’ Enables the write

Interface5-42 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)111011111F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

C141-E104-02EN viiManual OrganizationMHL2300AT, MHM2200AT,MHM2150AT, MHM2100ATDISK DRIVESPRODUCT MANUAL(C141-E104)<This manual>• Device Overvie

5.3 Host CommandsC141-E104-02EN 5-43Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0)00100 001 (X’21’: Mode 1)00100 010 (X’22’: Mode 2)Ul

Interface5-44 C141-E104-02ENAt command issuance (I/O registers setting contents)1F7H(CM)110001101F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F

5.3 Host CommandsC141-E104-02EN 5-45Word 47Bit 7-0 = 10:Word 59 = 0000:= 01xx:Maximum number of sectors that can be transferred per interruptby the R

Interface5-46 C141-E104-02ENAfter power on and the occurrence of a hard reset, the host can issue thiscommand only once when VV bit = 1. If this comma

5.3 Host CommandsC141-E104-02EN 5-47At command issuance (I/O registers setting contents)1F7H(CM)111110011F6H(DH) x L x DV xx1F5H(CH)1F4H(CL)1F3H(SN)x

Interface5-48 C141-E104-02ENIf the device is in the Set Max Locked or Set Max Freeze Locked state:51h, 04h: ABORTED commandAt command issuance (I/O r

5.3 Host CommandsC141-E104-02EN 5-49If this command is accepted in the Set Max Unlocked state, the device terminatesnormally.The READ NATIVE MAX ADDR

Interface5-50 C141-E104-02ENThe READ NATIVE MAX ADDRESS command is not executed just before thiscommand. The command is the SET MAX ADDRESS command i

5.3 Host CommandsC141-E104-02EN 5-51At command issuance (I/O registers setting contents)1F7H(CM)111110001F6H(DH) x L x DV xx1F5H(CH)1F4H(CL)1F3H(SN)1

Interface5-52 C141-E104-02ENWhen device 1 is not present:• The device 0 posts only the results of its own self-diagnosis.• The device 0 clears the BSY

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5.3 Host CommandsC141-E104-02EN 5-53At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DVHead No. /LB

Interface5-54 C141-E104-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x L x DV Head No. /LBA [MSB]1

5.3 Host CommandsC141-E104-02EN 5-55At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x L x DV Head No. /L

Interface5-56 C141-E104-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F

5.3 Host CommandsC141-E104-02EN 5-57At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1

Interface5-58 C141-E104-02ENattention: The automatic power-down is executed if no command is coming for30 min.At command issuance (I/O registers setti

5.3 Host CommandsC141-E104-02EN 5-59At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1

Interface5-60 C141-E104-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H(CL)1F

5.3 Host CommandsC141-E104-02EN 5-61(27) SLEEP (X’99’ or X’E6’)This command is the only way to make the device enter the sleep mode.Upon receipt of

Interface5-62 C141-E104-02EN(28) CHECK POWER MODE (X’98’ or X’E5’)The host checks the power mode of the device with this command.The host system can

C141-E104-02EN ixContentsCHAPTER 1 Device Overview ... 1-11.1 Features 1-21.1.

5.3 Host CommandsC141-E104-02EN 5-63(29) SMART (X’B0)This command performs operations for device failure predictions according to asubcommand specif

Interface5-64 C141-E104-02ENTable 5.7 Features Register values (subcommands) and functions (1 of 3)Features Resister FunctionX’D0’ SMART Read Attribut

5.3 Host CommandsC141-E104-02EN 5-65Table 5.7 Features Register values (subcommands) and functions (2 of 3)Features Resister FunctionX’D5’ SMART Read

Interface5-66 C141-E104-02ENTable 5.7 Features Register values (subcommands) and functions (3 of 3)Features Resister FunctionX’DA’ SMART Return Status

5.3 Host CommandsC141-E104-02EN 5-67At command completion (I-O registers setting contents)1F7H(ST) Status information1F6H(DH) x x x DV xx1F5H(CH)1F4H

Interface5-68 C141-E104-02ENTable 5.8 Format of device attribute value dataByte Item0001Data format version number02 Attribute 1 Attribute ID0304Statu

5.3 Host CommandsC141-E104-02EN 5-69• Data format version numberThe data format version number indicates the version number of the dataformat of the

Interface5-70 C141-E104-02EN• Current attribute valueThe current attribute value is the normalized raw attribute data. The valuevaries between 01h a

5.3 Host CommandsC141-E104-02EN 5-71Self-testexecution statusMeaning0 Self-test has been completed normally or has not beenexecuted.1 Self-test has b

Interface5-72 C141-E104-02EN• Check sumTwo’s complement of the lower byte, obtained by adding 511-byte data onebyte at a time from the beginning.• I

Contentsx C141-E104-02ENCHAPTER 3 Installation Conditions...3-13.1 Dimensions 3-23.2 Mo

5.3 Host CommandsC141-E104-02EN 5-73Table 5.10 SMART error log data format (2/2)Byte Item44 Error log 1 Error data Device/Head register45 Status re

Interface5-74 C141-E104-02ENStatus Meaning0 Unclear status1 Sleep status2 Standby status3 Active status or idle status (BSY bit = 0)4 Off-line data co

5.3 Host CommandsC141-E104-02EN 5-75(30) SECURITY DISABLE PASSWORD (F6h)This command invalidates the user password already set and releases the lock

Interface5-76 C141-E104-02ENTable 5.12 Contents of security passwordWord Contents0 Control wordBit 0: Identifier0 = Compares the user passwords.1 = C

5.3 Host CommandsC141-E104-02EN 5-77At command issuance (I-O register contents)1F7h(CM)111100111F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F

Interface5-78 C141-E104-02ENAt command issuance (I-O register contents)1F7h(CM)111101001F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F1h(FR)xxx

5.3 Host CommandsC141-E104-02EN 5-79• READ DMA • WRITE DMA • SECURITY DISABLE PASSWORD• READ LONG • WRITE LONG • SECURITY FREEZE LOCK• READ MU

Interface5-80 C141-E104-02EN(34) SECURITY SET PASSWORD (F1h)This command enables a user password or master password to be set.The host transfers the

5.3 Host CommandsC141-E104-02EN 5-81At command issuance (I-O register contents)1F7h(CM)111100011F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F

Interface5-82 C141-E104-02ENLOCKED MODE canceled (in UNLOCK MODE) has no affect on the UNLOCKcounter.Issuing this command in FROZEN MODE returns the A

ContentsC141-E104-02EN xi4.6.2 Write circuit 4-114.6.3 Read circuit 4-134.6.4 Digital PLL circuit 4-144.7 Servo Control 4-154.7.1 Serv

5.3 Host CommandsC141-E104-02EN 5-83At command issuance (I-O register contents)1F7h(CM)111001111F6h(DH) x x x DV xx1F5h(CH)1F4h(CL)1F3h(SN)1F2h(SC)1F

Interface5-84 C141-E104-02ENTable 5.15 Command code and parameters (2 of 2)Command name Error register (X’1F1’) Status register (X’1F7’)ICRC UNC INDF

5.4 Command ProtocolC141-E104-02EN 5-855.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0prior to

Interface5-86 C141-E104-02ENwords, the host should receive the relevant sector of data (512 bytes of uninsureddummy data) or release the DRQ status by

5.4 Command ProtocolC141-E104-02EN 5-87Note that the host does not need to read the Status register for thereading of a single sector or the last sec

Interface5-88 C141-E104-02ENa) The host writes any required parameters to the Features, Sector Count, SectorNumber, Cylinder, and Device/Head register

5.4 Command ProtocolC141-E104-02EN 5-89IMPORTANTFor transfer of a sector of data, the host needs to read Status register(X’1F7’) in order to clear IN

Interface5-90 C141-E104-02ENFigure 5.6 Protocol for the command execution without data transfer5.4.4 Other commands• READ MULTIPLE• SLEEP• WRITE MUL

5.5 Ultra DMA Feature SetC141-E104-02EN 5-91f) When the command execution is completed, the device clears both BSY andDRQ bits and asserts the INTRQ

Interface5-92 C141-E104-02EN5.5 Ultra DMA Feature Set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and WRITEDMA commands.

Contentsxii C141-E104-02EN5.5.2.1 Ultra DMA burst initiation phase 5-935.5.2.2 Data transfer phase 5-945.5.2.3 Ultra DMA burst termination pha

5.5 Ultra DMA Feature SetC141-E104-02EN 5-93Both the host and device perform a CRC function during an Ultra DMA burst. Atthe end of an Ultra DMA burs

Interface5-94 C141-E104-02ENg) Ultra DMA data in burstThe device should not invert the state of this signal in the period from themoment of STOP signa

5.5 Ultra DMA Feature SetC141-E104-02EN 5-95f) Once the transmitting side has outputted the ending request, the output stateof STROBE signal should no

Interface5-96 C141-E104-02ENhost shall not change the state of either signal until after receiving the firsttransition of DSTROBE from the device (i.e

5.5 Ultra DMA Feature SetC141-E104-02EN 5-97b) Host pausing an Ultra DMA data in burst1) The host shall not pause an Ultra DMA burst until at least on

Interface5-98 C141-E104-02EN7) If DSTROBE is negated, the device shall assert DSTROBE within tLIafter the host has asserted STOP. No data shall be tr

5.5 Ultra DMA Feature SetC141-E104-02EN 5-995) The host shall assert STOP no sooner than tRP after negatingHDMARDY-. The host shall not negate STOP a

Interface5-100 C141-E104-02EN5.5.4 Ultra DMA data out commands5.5.4.1 Initiating an Ultra DMA data out burstThe following steps shall occur in the ord

5.5 Ultra DMA Feature SetC141-E104-02EN 5-101HSTROBE edge no more frequently than tCYC for the selected Ultra DMAMode. The host shall not generate tw

Interface5-102 C141-E104-02EN5.5.4.4 Terminating an Ultra DMA data out bursta) Host terminating an Ultra DMA data out burstThe following stops shall o

ContentsC141-E104-02EN xiii6.1.1 Response to power-on 6-26.1.2 Response to hardware reset 6-46.1.3 Response to software reset 6-56.1.4 Res

5.5 Ultra DMA Feature SetC141-E104-02EN 5-103b) Device terminating an Ultra DMA data out burstThe following steps shall occur in the order they are li

Interface5-104 C141-E104-02EN13) The host shall neither negate STOP nor HSTROBE until at least tACK afternegating DMACK-.14) The host shall not assert

5.5 Ultra DMA Feature SetC141-E104-02EN 5-105Note: Since no bit clock is available, the recommended approach forcalculating CRC is to use a word cloc

Interface5-106 C141-E104-02EN5.5.6 Series termination required for Ultra DMASeries termination resistors are required at both the host and the device

5.6 TimingC141-E104-02EN 5-1075.6 Timing5.6.1 PIO data transferFigure 5.10 shows of the data transfer timing between the device and the hostsystem.

Interface5-108 C141-E104-02ENFigure 5.10 Data transfer timing

5.6 TimingC141-E104-02EN 5-1095.6.2 Multiword DMA data transferFigure 5.11 shows the multiword DMA data transfer timing between the deviceand the hos

Interface5-110 C141-E104-02EN5.6.3 Transfer of Ultra DMA dataFigures 5.12 to 5.21 define the timings concerning every phase for the Ultra DMABurst.Tab

5.6 TimingC141-E104-02EN 5-1115.6.3.2 Ultra DMA data burst timing requirementsTable 5.18 Ultra DMA data burst timing requirements (1 of 2)NAME MODE 0

Interface5-112 C141-E104-02ENTable 5.18 Ultra DMA data burst timing requirements (2 of 2)NAME MODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE

Contentsxiv C141-E104-02ENIllustrationsFiguresFigure 1.1 Current fluctuation (Typ.) at +5V when power is turned on 1-7Figure 2.1 Disk drive outerv

5.6 TimingC141-E104-02EN 5-1135.6.3.3 Sustained Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.No

Interface5-114 C141-E104-02EN5.6.3.4 Host pausing an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Mode

5.6 TimingC141-E104-02EN 5-1155.6.3.5 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra

Interface5-116 C141-E104-02EN5.6.3.6 Host terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA

5.6 TimingC141-E104-02EN 5-1175.6.3.7 Initiating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Mod

Interface5-118 C141-E104-02EN5.6.3.8 Sustained Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Not

5.6 TimingC141-E104-02EN 5-1195.6.3.9 Device pausing an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA

Interface5-120 C141-E104-02EN5.6.3.10 Host terminating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DM

5.6 TimingC141-E104-02EN 5-1215.6.3.11 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra

Interface5-122 C141-E104-02EN5.6.4 Power-on and resetFigure 5.22 shows power-on and reset (hardware and software reset) timing.(1) Only master device

C141-E104-02ENFOR SAFE OPERATIONHandling of This ManualThis manual contains important information for using this product. Read thoroughly before usin

ContentsC141-E104-02EN xvFigure 5.3 Read Sector(s) command protocol 5-86Figure 5.4 Protocol for command abort 5-87Figure 5.5 WRITE SECTOR(S) c

C141-E104-02EN 6-1CHAPTER 6 Operations6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cache6.

Operations6-2 C141-E104-02EN6.1 Device Response to the ResetThis section describes how the PDIAG- and DASP- signals responds when thepower of the IDD

6.1 Device Response to the ResetC141-E104-02EN 6-3Max. 31 sec.Max. 400 ms.Max. 30 sec.Max. 1 ms.If presence of a slave device isconfirmed, PDIAG- is

Operations6-4 C141-E104-02EN6.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to thepower-on reset.

6.1 Device Response to the ResetC141-E104-02EN 6-56.1.3 Response to software resetThe master device does not check the DASP- signal for a software re

Operations6-6 C141-E104-02EN6.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTICcommand and the slave devi

6.2 Address TranslationC141-E104-02EN 6-76.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium,the IDD al

Operations6-8 C141-E104-02EN6.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head(PH) 0, and

6.3 Power SaveC141-E104-02EN 6-9(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0,physical head 0, and physical

Operations6-10 C141-E104-02ENThe drive moves from the Active mode to the idle mode by itself.Regardless of whether the power down is enabled, the devi

Contentsxvi C141-E104-02ENTable 4.1 Self-calibration execution timechart 4-10Table 4.2 Write precompensation algorithm 4-11Table 5.1 Signal as

6.4 Defect ManagementC141-E104-02EN 6-11When one of following commands is issued, the command is executed normallyand the device is still stayed in t

Operations6-12 C141-E104-02EN6.4.1 Spare areaFollowing two types of spare area are provided for every physical head.1) Spare cylinder for sector slip:

6.4 Defect ManagementC141-E104-02EN 6-13(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder

Operations6-14 C141-E104-02ENAn unrecoverable write error occurs during write error retry, automatic alternateassignment is performed.6.5 Read-Ahead C

6.5 Read-Ahead CacheC141-E104-02EN 6-15• READ SECTOR (S)• READ MULTIPLE• READ DMAWhen caching operation is disabled by the SET FEATURES command, noca

Operations6-16 C141-E104-02EN− READ MULTIPLE− WRITE SECTOR(S)− WRITE MULTIPLE− WRITE VERIFY SECTOR(S)3) Caching operation is inhibited by the SET

6.5 Read-Ahead CacheC141-E104-02EN 6-172) Transfers the requested data that already read to the host system with readingthe requested data from the di

Operations6-18 C141-E104-02EN1) At receiving the sequential read command, the disk drive sets the DAP andHAP to the start address of the segment and r

6.5 Read-Ahead CacheC141-E104-02EN 6-19b. Sequential hitWhen the previously executed read command is the sequential commandand the last sector address

Operations6-20 C141-E104-02EN4) Finally, the cache data in the buffer is as follows.Read-ahead datac. Non-sequential command immediately after sequent

C141-E104-02EN 1-1CHAPTER 1 Device Overview1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic Noi

6.5 Read-Ahead CacheC141-E104-02EN 6-213) The cache data for next read command is as follows.Cache data6.5.3.4 Partially hitA part of requested data i

Operations6-22 C141-E104-02EN3) The cache data for next read command is as follows.Cache data6.6 Write CacheThe write cache function of the drive make

6.6 Write CacheC141-E104-02EN 6-23The drive uses a cache data of the last write command as a read cache data. Whena read command is issued to the sa

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C141-E104-02EN GL-1GlossaryActuatorHead positioning assembly. The actuator consists of a voice coil motor and headarm. If positions the read-write (

GlossaryGL-2 C141-E104-02ENMTBFMean time between failures. The MTBF is calculated by dividing the totaloperation time (total power-on time) by the nu

GlossaryC141-E104-02EN GL-3StatusThe status is a piece of one-byte information posted from the drive to the hostwhen command execution is ended. The

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C141-E104-02EN AB-1Acronyms and AbbreviationsAABRT Aborted commandAIC Automatic idle controlAMNF Address mark not foundATA AT attachmentAWG American w

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Device Overview1-2 C141-E104-02EN1.1 Features1.1.1 Functions and performanceThe following features of the MHL Series and MHM Series are described.(1)

C141-E104-02ENComment FormWe would appreciate your comments and suggestions regarding this manual.Manual code C141-E104-02ENManual name MHL2300AT, MHM

1.1 FeaturesC141-E104-02EN 1-31.1.3 Interface(1) Connection to interfaceWith the built-in ATA interface controller, the disk drives (the MHL Series a

Device Overview1-4 C141-E104-02EN1.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specifications of the disk drives (MHL Serie

1.3 Power RequirementsC141-E104-02EN 1-5Under the CHS mode (normal BIOS specification), formatted capacity,number of cylinders, number of heads, and

Device Overview1-6 C141-E104-02EN(3) Current Requirements and Power DissipationTable 1.3 lists the current and power dissipation.Table 1.3 Current and

1.4 Environmental SpecificationsC141-E104-02EN 1-7Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on(5) Power on/off sequenceThe vo

Device Overview1-8 C141-E104-02EN1.5 Acoustic NoiseTable 1.5 lists the acoustic noise specification.Table 1.5 Acoustic noise specificationItem Specifi

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1.7 ReliabilityC141-E104-02EN 1-91.7 Reliability(1) Mean time between failures (MTBF)Conditions of 300,000 h Power-on time 250H/month or less 3000H/

Device Overview1-10 C141-E104-02EN1.8 Error RateKnown defects, for which alternative blocks can be assigned, are not included inthe error rate count b

C141-E104-02EN 2-1CHAPTER 2 Device Configuration2.1 Device Configuration2.2 System ConfigurationThis chapter describes the internal configurations of

Device Configuration2-2 C141-E104-02EN2.1 Device ConfigurationFigure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE),read/

2.1 Device ConfigurationC141-E104-02EN 2-3MHL2300AT345Head120MHM2200AT3120HeadHeadMHM2100AT10MHM2150AT1203HeadFigure 2.2 Configuration of disk media

Device Configuration2-4 C141-E104-02EN2.2 System Configuration2.2.1 ATA interfaceFigures 2.3 and 2.4 show the ATA interface system configuration. The

2.2 System ConfigurationC141-E104-02EN 2-5IMPORTANTHA (host adaptor) consists of address decoder, driver, and receiver.ATA is an abbreviation of “AT

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C141-E104-02EN 3-1CHAPTER 3 Installation Conditions3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper SettingsThis chapter gives the external d

Installation Conditions3-2 C141-E104-02EN3.1 DimensionsFigure 3.1 illustrates the dimensions of the disk drive and positions of themounting screw hole

C141-E104-02ENRevision History(1/1)Edition Date Revised section (*1)(Added/Deleted/Altered)Details01 2000-02-15 — —02 2000-09-20 -Table 1.1- Table 1.2

3.1 DimensionsC141-E104-02EN 3-3Figure 3.1 Dimensions (MHM series) (2/2)

Installation Conditions3-4 C141-E104-02EN3.2 Mounting(1) OrientationFigure 3.2 illustrates the allowable orientations for the disk drive.

3.2 MountingC141-E104-02EN 3-5(2) FrameThe MR head bias of the HDD disk enclosure (DE) is zero. The mounting frameis connected to SG.IMPORTANTUse M3

Installation Conditions3-6 C141-E104-02ENIMPORTANTBecause of breather hole mounted to the HDD, do not allow this toclose during mounting.Locating of b

3.2 MountingC141-E104-02EN 3-7(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to theambient temperature

Installation Conditions3-8 C141-E104-02EN(5) Service areaFigure 3.6 shows how the drive must be accessed (service areas) during and afterinstallation.

3.2 MountingC141-E104-02EN 3-9- General notesFigure 3.7 Handling cautions- Installation(1) Please use the driver of a low impact when you use an ele

Installation Conditions3-10 C141-E104-02EN3.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for

3.3 Cable ConnectionsC141-E104-02EN 3-113.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors.T

Installation Conditions3-12 C141-E104-02EN3.3.4 Power supply connector (CN1)Figure 3.10 shows the pin assignment of the power supply connector (CN1).F

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3.4 Jumper SettingsC141-E104-02EN 3-133.4.2 Factory default settingFigure 3.12 shows the default setting position at the factory.Figure 3.12 Factory

Installation Conditions3-14 C141-E104-02EN3.4.4 CSEL settingFigure 3.14 shows the cable select (CSEL) setting.ShortOpenBD2AC1Note:The CSEL setting is

3.4 Jumper SettingsC141-E104-02EN 3-15Figure 3.16 Example (2) of Cable Selectdrive drive

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C141-E104-02EN 4-1CHAPTER 4 Theory of Device Operation4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on Sequence4.5 Self-calibration4.

Theory of Device Operation4-2 C141-E104-02EN4.1 OutlineThis chapter consists of two parts. First part (Section 4.2) explains mechanicalassemblies of

4.2 SubassembliesC141-E104-02EN 4-3MHL2300AT345Head120MHM2200AT3120HeadHeadMHK2100AT10MHM2150AT1203HeadFigure 4.1 Head structure4.2.3 SpindleThe spin

Theory of Device Operation4-4 C141-E104-02EN4.3 Circuit ConfigurationFigure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3

4.3 Circuit ConfigurationC141-E104-02EN 4-5Figure 4.2 Power Supply Configuration5V3.3V- 3VHDC SVC HDIC MCU FROMRDCSDRAM

Theory of Device Operation4-6 C141-E104-02ENFigure 4.3 Circuit ConfigurationRead DataMPU(MicroProcessorUnit)HDICHDC(Hard DiskController)FROMProgramMem

C141-E104-02EN iPrefaceThis manual describes the MHL Series and MHM Series, 2.5-inch hard disk drives.These drives have a built-in controller that is

4.3 Circuit ConfigurationC141-E104-02EN 4-74.4 Power-on SequenceFigure 4.4 describes the operation sequence of the disk drive at power-on. Theoutlin

Theory of Device Operation4-8 C141-E104-02ENFigure 4.4 Power-on operation sequence4.5 Self-calibrationThe disk drive occasionally performs self-calibr

4.5 Self-calibrationC141-E104-02EN 4-9The forces are compensated by adding the measured value to the specified currentvalue to the power amplifier.

Theory of Device Operation4-10 C141-E104-02ENTable 4.1 Self-calibration execution timechartTime elapsed Time elapsed(accumulated)1 At power-on Initial

4.6 Read/write CircuitC141-E104-02EN 4-114.6.2 Write circuitThe write data is output from the hard disk controller (HDC) with the NRZ dataformat, and

Theory of Device Operation4-12 C141-E104-02ENFigure 4.5 Read/write circuit block diagramHDICWDX/WDY

4.6 Read/write CircuitC141-E104-02EN 4-134.6.3 Read circuitThe head read signal from the PreAMP is regulated by the automatic gain control(AGC) circu

Theory of Device Operation4-14 C141-E104-02EN(3) Flash digitizer circuitThis circuit is 10-tap sampled analog transversal filter circuit that cosine-e

4.6 Read/write CircuitC141-E104-02EN 4-154.7 Servo ControlThe actuator motor and the spindle motor are submitted to servo control. Theactuator motor

Theory of Device Operation4-16 C141-E104-02ENThe major internal operations are listed below.a. Spindle motor startStarts the spindle motor and acceler

Prefaceii C141-E104-02ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alertmessage consists

4.7 Servo ControlC141-E104-02EN 4-17 (2) Servo burst capture circuitThe servo burst capture circuit reproduces signals (position signals) that indica

Theory of Device Operation4-18 C141-E104-02EN4.7.2 Data-surface servo formatFigure 4.8 describes the physical layout of the servo frame. The three ar

4.7 Servo ControlC141-E104-02EN 4-19Figure 4.8 Physical sector servo configuration on disk surface W/R Recovery Servo Mark Gray CodeW/R RecoveryServo

Theory of Device Operation4-20 C141-E104-02EN4.7.3 Servo frame formatAs the servo information, the IDD uses the two-phase servo generated from thegray

4.7 Servo ControlC141-E104-02EN 4-21(1) Write/read recoveryThis area is used to absorb the write/read transient and to stabilize the AGC.(2) Servo ma

Theory of Device Operation4-22 C141-E104-02ENd) If the head is stopped at the reference cylinder from there. Track followingcontrol starts.(2) Seek o

4.7 Servo ControlC141-E104-02EN 4-23d) During phase switching, the spindle motor starts rotating in low speed, andgenerates a counter electromotive f

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C141-E104-02EN 5-1CHAPTER 5 Interface5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA Feature Set5.6 Timi

Interface5-2 C141-E104-02EN5.1 Physical Interface5.1.1 Interface signalsFigure 5.1 shows the interface signals.Figure 5.1 Interface signalsDATA 0-15:

PrefaceC141-E104-02EN iiiLiability Exception“Disk drive defects” refers to defects that involve adjustment, repair, orreplacement.Fujitsu is not liabl

5.1 Physical InterfaceC141-E104-02EN 5-35.1.2 Signal assignment on the connectorTable 5.1 shows the signal assignment on the interface connector.Tabl

Interface5-4 C141-E104-02EN[signal] [I/O] [Description]ENCSEL I This signal is used to set master/slave using the CSEL signal (pin 28).Pins B and D Op

5.1 Physical InterfaceC141-E104-02EN 5-5[signal] [I/O] [Description]CS0- I Chip select signal decoded from the host address bus. This signalis used

Interface5-6 C141-E104-02EN[signal] [I/O] [Description]DMARQ O This signal is used for DMA transfer between the host system andthe device. The device

5.2 Logical InterfaceC141-E104-02EN 5-75.2.1 I/O registersCommunication between the host system and the device is done through input-output (I/O) reg

Interface5-8 C141-E104-02EN5.2.2 Command block registers(1) Data register (X’1F0’)The Data register is a 16-bit register for data block transfer betwe

5.2 Logical InterfaceC141-E104-02EN 5-9[Diagnostic code]X’01’: No Error Detected.X’02’: HDC Register Compare ErrorX’03’: Data Buffer Compare Error.X’

Interface5-10 C141-E104-02EN(6) Cylinder Low register (X’1F4’)The contents of this register indicates low-order 8 bits of the starting cylinderaddress

5.2 Logical InterfaceC141-E104-02EN 5-11(9) Status register (X’1F7’)The contents of this register indicate the status of the device. The contents of

Interface5-12 C141-E104-02EN- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault(write fault) condition has been detected

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5.3 Host CommandsC141-E104-02EN 5-135.2.3 Control block registers(1) Alternate Status register (X’3F6’)The Alternate Status register contains the sam

Interface5-14 C141-E104-02ENWhen the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the datatransfer) and the host system writes to the co

5.3 Host CommandsC141-E104-02EN 5-15Table 5.3 Command code and parameters (2 of 2)Command code (Bit) Parameters used76543210FRSCSNCYDHIDLE IMMEDIATE

Interface5-16 C141-E104-02ENY*: Necessary to set parameters under the LBA mode.N: Not necessary to set parameters (The parameter is ignored if it is s

5.3 Host CommandsC141-E104-02EN 5-17CM: Command register FR: Features registerDH: Device/Head register ST: Status registerCH: Cylinder High regi

Interface5-18 C141-E104-02ENCommand block registers contain the cylinder, the head, and the sector addressesof the sector (in the CHS mode) or the log

5.3 Host CommandsC141-E104-02EN 5-19The implementation of the READ MULTIPLE command is identical to that of theREAD SECTOR(S) command except that the

Interface5-20 C141-E104-02ENFigure 5.2 Execution example of READ MULTIPLE commandAt command issuance (I/O registers setting contents)1F7H(CM)110001001

5.3 Host CommandsC141-E104-02EN 5-21(3) READ DMA (X’C8’ or X’C9’)This command operates similarly to the READ SECTOR(S) command except forfollowing ev

Interface5-22 C141-E104-02ENAt command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH) x L x DV End head No. /LBA [M