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5.5 Ultra DMA Feature Set
C141-E104-02EN 5-103
b) Device terminating an Ultra DMA data out burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.4.11 and 5.6.4.2 for specific timing
requirements):
1) The device shall not initiate Ultra DMA burst termination until at least
one data word of an Ultra DMA burst has been transferred.
2) The device shall initiate Ultra DMA burst termination by negating
DDMARDY-.
3) The host shall stop generating an HSTROBE edges within t
RFS
of the
device negating DDMARDY-.
4) If the device negates DDMARDY- within t
SR
after the host has generated
an HSTROBE edge, then the device shall be prepared to receive zero or
one additional data words. If the device negates DDMARDY- greater
than t
SR
after the host has generated an HSTROBE edge, then the device
shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and t
RFS
timing for the host.
5) The device shall negate DMARQ no sooner than t
RP
after negating
DDMARDY-. The device shall not assert DMARQ again until after the
Ultra DMA burst is terminated.
6) The host shall assert STOP with t
LI
after the device has negated
DMARQ. The host shall not negate STOP again until after the Ultra
DMA burst is terminated.
7) If HSTROBE is negated, the host shall assert HSTROBE with t
LI
after
the device has negated DMARQ. No data shall be transferred during this
assertion. The device shall ignore this transition of HSTROBE.
HSTROBE shall remain asserted until the Ultra DMA burst is
terminated.
8) The host shall place the result of its CRC calculation on DD (15:0) (see
5.5.5).
9) The host shall negate DMACK- no sooner than t
MLI
after the host has
asserted HSTROBE and STOP and the device has negated DMARQ and
DDMARDY-, and no sooner than t
DVS
after placing the result of its CRC
calculation on DD (15:0).
10) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
11) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA bursts for any one command, at the end of the
command, the device shall report the first error that occurred (see 5.5.5).
12) The device shall release DDMARDY- within t
IORDYZ
after the host has
negated DMACK-.
- MHL2300AT, MHM2200AT 1
- MHM2150AT, MHM2100AT 1
- DISK DRIVES 1
- PRODUCT MANUAL 1
- FOR SAFE OPERATION 2
- Revision History 4
- Overview of Manual 6
- Operating Environment 7
- Attention 7
- Liability Exception 8
- Important Alert Items 10
- Manual Organization 12
- Contents 14
- Illustrations 19
- CHAPTER 1 Device Overview 22
- 1.1 Features 23
- 1.1.3 Interface 24
- 1.2 Device Specifications 25
- 1.3 Power Requirements 26
- 1.5 Acoustic Noise 29
- 1.6 Shock and Vibration 29
- 1.7 Reliability 30
- 1.8 Error Rate 31
- 1.9 Media Defects 31
- C141-E104-02EN 2-1 32
- 2.1 Device Configuration 32
- 2.2 System Configuration 32
- 3.1 Dimensions 39
- 3.1 Dimensions 40
- C141-E104-02EN 3-3 40
- 3.2 Mounting 41
- 3.2 Mounting 46
- C141-E104-02EN 3-9 46
- Figure 3.7 Handling cautions 46
- 3.3 Cable Connections 47
- 3.3.3 Device connection 48
- 3.4 Jumper Settings 49
- 3.4.2 Factory default setting 50
- 3.4.4 CSEL setting 51
- 3.4 Jumper Settings 52
- C141-E104-02EN 3-15 52
- 4.1 Outline 55
- 4.2 Subassemblies 55
- 4.2.3 Spindle 56
- 4.2.4 Actuator 56
- 4.2.5 Air filter 56
- 4.3 Circuit Configuration 57
- Theory of Device Operation 59
- 4-6 C141-E104-02EN 59
- 4.4 Power-on Sequence 60
- 4.5 Self-calibration 61
- • The power is turned on 62
- 4.6 Read/write Circuit 63
- 4.6.2 Write circuit 64
- 4-12 C141-E104-02EN 65
- 4.6.3 Read circuit 66
- 4.6.4 Digital PLL circuit 67
- 4.7 Servo Control 68
- 4.7.3 Servo frame format 73
- 4.7.4 Actuator motor control 74
- 4.7.5 Spindle motor control 75
- CHAPTER 5 Interface 78
- 5.1 Physical Interface 79
- − assertion of RESET- signal 81
- 5.2 Logical Interface 83
- 5.2.1 I/O registers 84
- 5.2.2 Command block registers 85
- 5.3 Host Commands 90
- 5.3.2 Command descriptions 93
- Password information 124
- (CM) 11110100 132
- • Data format version number 146
- • Attribute ID 146
- • Current attribute value 147
- • Raw attribute value 147
- • Self test execution status 147
- • Error logging capability 148
- • Check sum 149
- • Error data 150
- • Status 150
- • Self test log 1 to 21 151
- • Self test index 151
- • SECURITY SET PASSWORD 155
- • SECURITY UNLOCK 155
- • SECURITY DISABLE PASSWORD 155
- • SECURITY ERASE UNIT 155
- 5.3.3 Error posting 160
- Interface 161
- 5-84 C141-E104-02EN 161
- 5.4 Command Protocol 162
- IMPORTANT 163
- 5.4.4 Other commands 167
- 5.5 Ultra DMA Feature Set 169
- 5.5.2 Phases of operation 170
- 5.6 Timing 184
- 5-108 C141-E104-02EN 185
- 5.6 Timing 186
- C141-E104-02EN 5-109 186
- C141-E104-02EN 5-111 188
- 5-112 C141-E104-02EN 189
- 5.6.4 Power-on and reset 199
- CHAPTER 6 Operations 200
- 6.1.1 Response to power-on 201
- C141-E104-02EN 6-3 202
- 6.2 Address Translation 206
- 6.2.2 Logical address 207
- 6.3 Power Save 208
- 6.4 Defect Management 210
- 6.4.1 Spare area 211
- 1234567 505 506 212
- 1234567 505 506(unused) 212
- 6.5 Read-Ahead Cache 213
- • READ SECTOR (S) 214
- 6.5.3 Usage of read segment 215
- 6.6 Write Cache 221
- Glossary 224
- Acronyms and Abbreviations 228
- Comment Form 230
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