Contents
xii C141-E104-02EN
5.5.2.1 Ultra DMA burst initiation phase 5-93
5.5.2.2 Data transfer phase 5-94
5.5.2.3 Ultra DMA burst termination phase 5-94
5.5.3 Ultra DMA data in commands 5-95
5.5.3.1 Initiating an Ultra DMA data in burst 5-95
5.5.3.2 The data in transfer 5-96
5.5.3.3 Pausing an Ultra DMA data in burst 5-96
5.5.3.4 Terminating an Ultra DMA data in burst 5-97
5.5.4 Ultra DMA data out commands 5-100
5.5.4.1 Initiating an Ultra DMA data out burst 5-100
5.5.4.2 The data out transfer 5-100
5.5.4.3 Pausing an Ultra DMA data out burst 5-101
5.5.4.4 Terminating an Ultra DMA data out burst 5-102
5.5.5 Ultra DMA CRC rules 5-104
5.5.6 Series termination required for Ultra DMA 5-106
5.6 Timing 5-107
5.6.1 PIO data transfer 5-107
5.6.2 Multiword DMA data transfer 5-109
5.6.3 Transfer of Ultra DMA data 5-110
5.6.3.1 Starting of Ultra DMA data In Burst 5-110
5.6.3.2 Ultra DMA data burst timing requirements 5-111
5.6.3.3 Sustained Ultra DMA data in burst 5-113
5.6.3.4 Host pausing an Ultra DMA data in burst 5-114
5.6.3.5 Device terminating an Ultra DMA data in burst 5-115
5.6.3.6 Host terminating an Ultra DMA data in burst 5-116
5.6.3.7 Initiating an Ultra DMA data out burst 5-117
5.6.3.8 Sustained Ultra DMA data out burst 5-118
5.6.3.9 Device pausing an Ultra DMA data out burst 5-119
5.6.3.10 Host terminating an Ultra DMA data out burst 5-120
5.6.3.11 Device terminating an Ultra DMA data in burst 5-121
5.6.4 Power-on and reset 5-122
CHAPTER 6 Operations .................................................................................6-1
6.1 Device Response to the Reset 6-2
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