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5.3 Host Commands
(19) WRITE MULTIPLE (X’C5’)
This command is similar to the WRITE SECTOR(S) command. The device does
not generate interrupts (assertion of the INTRQ) signal) on each sector but on the
transfer of a block which contains the number of sectors for which the number is
defined by the SET MULTIPLE MODE command. The DRQ bit of the Status
register is required to set only at the start of the data block, not on each sector.
The number of sectors per block is defined by a successful SET MULTIPLE
MODE command. The SET MULTIPLE MODE command should be executed
prior to the WRITE MULTIPLE command.
If the number of requested sectors is not divided evenly (having the same number
of sectors [block count]), as many full blocks as possible are transferred, then a
final partial block is transferred. The number of sectors in the partial block to be
transferred is n where n = remainder of (“number of sectors”/”block count”).
If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE
command is executed or when WRITE MULTIPLE command is disabled, the
device rejects the WRITE MULTIPLE command with an ABORTED
COMMAND error.
Disk errors encountered during execution of the WRITE MULTIPLE command are
posted after attempting to write the block or the partial block that was transferred.
Write operation ends at the sector where the error was encountered even if the sector
is in the middle of a block. If an error occurs, the subsequent block shall not be
transferred. Interrupts are generated when the DRQ bit of the Status register is set at
the beginning of each block or partial block.
The contents of the command block registers related to addresses after the transfer
of a data block containing an erred sector are undefined. To obtain a valid error
information, the host should retry data transfer as an individual request.
At command issuance (I/O registers setting contents)
1F7
H
(CM) 1 1 0 0 0 1 0 1
1F6
H
(DH) x L x DV Start head No. / LBA
[MSB]
1F5
H
(CH)
1F4
H
(CL)
1F3
H
(SN)
1F2
H
(SC)
1F1
H
(FR)
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
C141-E258 5-65
- MHW2060AC, MHW2040AC 1
- DISK DRIVES 1
- PRODUCT MANUAL 1
- FOR SAFE OPERATION 2
- Revision History 3
- Preface 5
- Operating Environment 6
- Conventions 6
- Attention 7
- Liability Exception 7
- Important Alert Items 9
- Manual Organization 11
- Contents 13
- Illustrations 19
- CHAPTER 1 Device Overview 23
- 1.1 Features 24
- 1.1.3 Interface 25
- 1.2 Device Specifications 26
- 1.3 Power Requirements 29
- 1.5 Acoustic Noise 33
- 1.6 Shock and Vibration 33
- 1.7 Reliability 34
- 1.8 Error Rate 35
- 1.9 Media Defects 35
- 1.10 Load/Unload Function 35
- 2.1 Device Configuration 40
- 2.2 System Configuration 41
- 2.2.3 2 drives connection 42
- 3.1 Dimensions 44
- 3.2 Mounting 45
- Connector 50
- 3.3.3 Device connection 51
- 3.4 Jumper Settings 52
- 3.4.4 CSEL setting 54
- 4.1 Outline 58
- 4.2 Subassemblies 58
- 4.3 Circuit Configuration 59
- C141-E258 4-5 61
- 4.4 Power-on Sequence 62
- 4.5 Self-calibration 63
- 4.6 Read/write Circuit 65
- 4.6.3 Read circuit 66
- 4.6.4 Digital PLL circuit 67
- 4.7 Servo Control 68
- Theory of Device Operation 72
- 4-16 C141-E258 72
- 4.7.3 Servo frame format 73
- 4.7.5 Spindle motor control 75
- CHAPTER 5 Interface 77
- 5.1 Physical Interface 78
- 5.2 Logical Interface 82
- 5.2.1 I/O registers 83
- 5.3 Host Commands 90
- 5.3.2 Command descriptions 94
- • Default function 110
- • Unload Feature: 110
- • Attribute ID 123
- • Raw attribute value 124
- • Status Flag 124
- • Current attribute value 124
- • Error logging capability 127
- • Check sum 127
- • SMART error logging 128
- • Command data structure 130
- • Error data structure 130
- • Status 130
- • SMART self-test 131
- • Self-test number 131
- • Self-test index 131
- • Test span 132
- • Current LBA under test 132
- • Current span under test 132
- • Feature Flags 133
- (CM) 1 1 1 0 0 1 0 0 149
- • SET MAX ADDRESS 180
- Password information 182
- • SET MAX SET PASSWORD 184
- • SET MAX LOCK 184
- • SET MAX UNLOCK 184
- • Description 186
- 5.3.3 Error posting 203
- Interface 204
- 5-128 C141-E258 204
- 5.4 Command Protocol 205
- (*) Transfers dummy data 207
- 5.4.4 Other commands 211
- 5.5 Ultra DMA Feature Set 213
- 5.5.2 Phases of operation 214
- 5.5.5 Ultra DMA CRC rules 223
- 5.6 Timing 225
- 5.6.4 Power-on and reset 240
- CHAPTER 6 Operations 241
- 6.1.1 Response to power-on 242
- 6.2 Power Save 247
- 6.3 Defect Processing 249
- Sector (physical) 250
- Cylinder 0 250
- (Not used) 250
- 779 780 251
- 6.4 Read-ahead Cache 252
- For MPU work For R/W command 252
- 8,388,608 bytes 252
- 6.4.2 Caching operation 253
- 256
- 6.5 Write Cache 258
- Glossary 261
- Acronyms and Abbreviations 265
- Comment Form 273
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