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5.5 Ultra DMA Feature Set
assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
8) If the host has not placed the result of its CRC calculation on DD (15:0)
since first driving DD (15:0) during (6), the host shall place the result of
its CRC calculation on DD (15:0) (see 5.5.5).
9) The host shall negate DMACK- no sooner than t
MLI
after the device has
asserted DSTROBE and negated DMARQ and the host has asserted
STOP and negated HDMARDY-, and no sooner than t
DVS
after the host
places the result of its CRC calculation on DD (15:0).
10) The device shall latch the host's CRC data from DD (15:0) on the
negating edge of DMACK-.
11) The device shall compare the CRC data received from the host with the
results of its own CRC calculation. If a miscompare error occurs during
one or more Ultra DMA bursts for any one command, at the end of the
command the device shall report the first error that occurred (see 5.5.5).
12) The device shall release DSTROBE within t
IORDYZ
after the host negates
DMACK-.
13) The host shall not negate STOP no assert HDMARDY- until at least t
ACK
after negating DMACK-.
14) The host shall not assert DIOR-, CS0-, CS1-, DA2, DA1, or DA0 until at
least t
ACK
after negating DMACK.
b) Host terminating an Ultra DMA data in burst
The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.6 and 5.6.3.2 for specific timing requirements):
1) The host shall not initiate Ultra DMA burst termination until at least one
data word of an Ultra DMA burst has been transferred.
2) The host shall initiate Ultra DMA burst termination by negating
HDMARDY-. The host shall continue to negate HDMARDY- until the
Ultra DMA burst is terminated.
3) The device shall stop generating DSTROBE edges within t
RFS
of the host
negating HDMARDY-.
C141-E258 5-141
- MHW2060AC, MHW2040AC 1
- DISK DRIVES 1
- PRODUCT MANUAL 1
- FOR SAFE OPERATION 2
- Revision History 3
- Preface 5
- Operating Environment 6
- Conventions 6
- Attention 7
- Liability Exception 7
- Important Alert Items 9
- Manual Organization 11
- Contents 13
- Illustrations 19
- CHAPTER 1 Device Overview 23
- 1.1 Features 24
- 1.1.3 Interface 25
- 1.2 Device Specifications 26
- 1.3 Power Requirements 29
- 1.5 Acoustic Noise 33
- 1.6 Shock and Vibration 33
- 1.7 Reliability 34
- 1.8 Error Rate 35
- 1.9 Media Defects 35
- 1.10 Load/Unload Function 35
- 2.1 Device Configuration 40
- 2.2 System Configuration 41
- 2.2.3 2 drives connection 42
- 3.1 Dimensions 44
- 3.2 Mounting 45
- Connector 50
- 3.3.3 Device connection 51
- 3.4 Jumper Settings 52
- 3.4.4 CSEL setting 54
- 4.1 Outline 58
- 4.2 Subassemblies 58
- 4.3 Circuit Configuration 59
- C141-E258 4-5 61
- 4.4 Power-on Sequence 62
- 4.5 Self-calibration 63
- 4.6 Read/write Circuit 65
- 4.6.3 Read circuit 66
- 4.6.4 Digital PLL circuit 67
- 4.7 Servo Control 68
- Theory of Device Operation 72
- 4-16 C141-E258 72
- 4.7.3 Servo frame format 73
- 4.7.5 Spindle motor control 75
- CHAPTER 5 Interface 77
- 5.1 Physical Interface 78
- 5.2 Logical Interface 82
- 5.2.1 I/O registers 83
- 5.3 Host Commands 90
- 5.3.2 Command descriptions 94
- • Default function 110
- • Unload Feature: 110
- • Attribute ID 123
- • Raw attribute value 124
- • Status Flag 124
- • Current attribute value 124
- • Error logging capability 127
- • Check sum 127
- • SMART error logging 128
- • Command data structure 130
- • Error data structure 130
- • Status 130
- • SMART self-test 131
- • Self-test number 131
- • Self-test index 131
- • Test span 132
- • Current LBA under test 132
- • Current span under test 132
- • Feature Flags 133
- (CM) 1 1 1 0 0 1 0 0 149
- • SET MAX ADDRESS 180
- Password information 182
- • SET MAX SET PASSWORD 184
- • SET MAX LOCK 184
- • SET MAX UNLOCK 184
- • Description 186
- 5.3.3 Error posting 203
- Interface 204
- 5-128 C141-E258 204
- 5.4 Command Protocol 205
- (*) Transfers dummy data 207
- 5.4.4 Other commands 211
- 5.5 Ultra DMA Feature Set 213
- 5.5.2 Phases of operation 214
- 5.5.5 Ultra DMA CRC rules 223
- 5.6 Timing 225
- 5.6.4 Power-on and reset 240
- CHAPTER 6 Operations 241
- 6.1.1 Response to power-on 242
- 6.2 Power Save 247
- 6.3 Defect Processing 249
- Sector (physical) 250
- Cylinder 0 250
- (Not used) 250
- 779 780 251
- 6.4 Read-ahead Cache 252
- For MPU work For R/W command 252
- 8,388,608 bytes 252
- 6.4.2 Caching operation 253
- 256
- 6.5 Write Cache 258
- Glossary 261
- Acronyms and Abbreviations 265
- Comment Form 273
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