Fujitsu P4X-0036-2M-800L Datasheet Page 12
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Intel® Xeon™ Processor with 800 MHz System Bus
12 Datasheet
1.2 References
Material and concepts available in the following documents may be beneficial when reading this
document:
NOTE: Contact your Intel representative for the latest revision of documents without document numbers.
1.3 State of Data
The data contained within this document is subject to change. It is the most accurate information
available by the publication date of this document.
Document
Intel Document
Number
Intel® Extended Memory 64 Technology Software Developer's Manual, Volume 1
Intel® Extended Memory 64 Technology Software Developer's Manual, Volume 2
300834
300835
mPGA604 Socket Design Guidelines 254232
AP-485, Intel® Processor Identification and CPUID Instruction 241618
IA-32 Intel® Architecture Optimization Reference Manual 248966
IA-32 Intel® Architecture Software Developer's Manual, Volume 1: Basic Architecture
IA-32 Intel® Architecture Software Developer's Manual, Volume 2A: Instruction Set
Reference, A-M
IA-32 Intel® Architecture Software Developer's Manual, Volume 2B: Instruction Set
Reference, N-Z
IA-32 Intel® Architecture Software Developer's Manual, Volume 3: System Programming
Guide
253665
253666
253667
253668
ITP700 Debug Port Design Guide 249679
Intel® Xeon™ Processor with 800 MHz System Bus Specification Update 302402
Intel® Xeon™ Processor with 800 MHz System Bus Core Boundary Scan Descriptive
Language (BSDL) Model (V1.0) and Cell Descriptor File (V1.0)
302403
Intel® Xeon™ Processor with 800 MHz System Bus Thermal Models zip file
Intel® Xeon™ Processor with 800 MHz System Bus Mechanical Models (IGES) zip file
Intel® Xeon™ Processor with 800 MHz System Bus Mechanical Models (ProE*) zip file
Intel® Xeon™ Processor with 800 MHz System Bus Thermal / Mechanical Design Guide 302404
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0
Design Guidelines
302731
Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1
Design Guidelines
302732
- System Bus 1
- 2 Datasheet 2
- Contents 3
- Revision History 7
- 8 Datasheet 8
- 1.0 Introduction 9
- 1.1 Terminology 10
- 1.2 References 12
- 1.3 State of Data 12
- 2.1 Power and Ground Pins 13
- 2.2 Decoupling Guidelines 13
- 2.5 Reserved or Unused Pins 17
- Ω, then a value between 18
- Ω and 60 Ω should be used 18
- Datasheet 19 19
- 2.9 Mixing Processors 21
- SS -0.30 1.55 V 22
- Datasheet 23 23
- 24 Datasheet 24
- Datasheet 25 25
- 26 Datasheet 26
- Table 10. V 26
- 2.11.3 Die Voltage Validation 28
- 0 5 10 15 20 25 28
- VID - 0.000 28
- VID + 0.050 28
- Datasheet 29 29
- 30 Datasheet 30
- 3.0 Mechanical Specifications 31
- 32 Datasheet 32
- Datasheet 33 33
- 3.7 Processor Materials 35
- 3.8 Processor Markings 36
- Intel® Xeon™ 37
- Processor 37
- (800 MHz) 37
- 4.0 Signal Definitions 39
- 40 Datasheet 40
- Datasheet 41 41
- 42 Datasheet 42
- Datasheet 43 43
- 44 Datasheet 44
- Datasheet 45 45
- 46 Datasheet 46
- Datasheet 47 47
- 48 Datasheet 48
- 5.0 Pin List 49
- 5.1.1 Pin Listing by Pin Name 50
- Datasheet 51 51
- 52 Datasheet 52
- Datasheet 53 53
- 54 Datasheet 54
- Datasheet 55 55
- 56 Datasheet 56
- Datasheet 57 57
- 58 Datasheet 58
- Datasheet 59 59
- 60 Datasheet 60
- Datasheet 61 61
- 62 Datasheet 62
- Datasheet 63 63
- 64 Datasheet 64
- Datasheet 65 65
- 66 Datasheet 66
- 6.0 Thermal Specifications 67
- Power [W] T 70
- [°C] Power [W] T 70
- 6.1.2 Thermal Metrology 71
- 6.2.1 Thermal Monitor 71
- 6.2.2 On-Demand Mode 72
- 6.2.3 PROCHOT# Signal Pin 72
- 6.2.4 FORCEPR# Signal Pin 72
- 6.2.5 THERMTRIP# Signal Pin 73
- and Fan Speed Reduction 73
- 6.2.7 Thermal Diode 73
- 74 Datasheet 74
- 7.0 Features 75
- 7.2.1 Normal State 76
- 7.2.2 HALT Power-Down State 76
- 7.2.3 Stop-Grant State 76
- 7.2.5 Sleep State 77
- SpeedStep® Technology 78
- 8.1 Introduction 79
- 80 Datasheet 80
- 8.2 Mechanical Specifications 81
- 82 Datasheet 82
- Datasheet 83 83
- 84 Datasheet 84
- Datasheet 85 85
- 86 Datasheet 86
- Datasheet 87 87
- 88 Datasheet 88
- 8.3 Electrical Requirements 89
- 8.4 Thermal Specifications 92
- 8.5 Boxed Processor Contents 93
- 94 Datasheet 94
- 9.2.1 System Implementation 95
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