Fujitsu P4X-0036-2M-800L Datasheet download pdf (Page 23)

Intel® Xeon™ Processor with 800 MHz System Bus

Datasheet 23

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based on silicon

characterization, however they may be updated as further data becomes available. Listed frequencies are not necessarily

committed production frequencies.

2. Individual processor VID values may be calibrated during manufacturing such that two devices at the same speed may have

different VID settings.

3. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is

required. See Section 2.4 for more information.

4. The voltage specification requirements are measured across vias on the platform for the VCCSENSE and VSSSENSE pins

close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum

impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system

is not coupled in the scope probe.

5. Refer to Table 10 and corresponding Figure 4. The processor should not be subjected to any static V

level that exceeds the

CC_MAX

associated with any particular current. Failure to adhere to this specification can shorten processor lifetime.

6. Minimum V

and maximum I

are specified at the maximum processor case temperature (T

CASE

) shown in Table 23.

CC_MAX

is specified at the relative V

CC_MAX

point on the V

load line. The processor is capable of drawing I

CC_MAX

for up to

10 ms. Refer to Figure 2 for further details on the average processor current draw over various time durations.

Table 9. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

VID range VID range for Intel® Xeon™

processor with 800 MHz system bus

1.2875 1.4000 V 2,3

for Intel® Xeon™ processor

with 800 MHz system bus FMB

processor

See Table 10 and

Figure 4

VID - I

(max) * 1.25 mΩ V 3, 4, 5, 6, 7

VID

Transition

VID step size during a transition ±12.5 mV 8

Total allowable DC load line shift

from VID steps

450 mV 9

Front Side Bus termination voltage

(DC specification)

1.176 1.20 1.224 V 10

Front Side Bus termination voltage

(AC & DC specification)

1.140 1.20 1.260 V 10, 11

for Intel® Xeon™ processor with

800 MHz system bus with multiple

VIDs

2.80 - 3.60 GHz

FMB

100

120

6, 19

6, 7, 20

Front Side Bus end-agent V

current

4.8 A 12

Front Side Bus mid-agent V

current

1.5 A 13

CC_VCCA

for PLL power pins 120 mA 14

CC_VCCIOPLL

for PLL power pins 100 mA 14

CC_GTLREF

for GTLREF pins 200 µA 15

SGNT

SLP

Stop Grant for Intel® Xeon™

processor with 800 MHz system bus

2.80 GHz - FMB

A7,16

TCC

TCC Active I

A17

CC_TDC

for Intel® Xeon™ processor with

800 MHz system bus

Thermal Design Current

2.80 - 3.60 GHz

FMB

105

18,19

7,18,20

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 95 96

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