Fujitsu P4X-0036-2M-800L Datasheet download pdf (Page 13)

Intel® Xeon™ Processor with 800 MHz System Bus

Datasheet 13

2.0 Electrical Specifications

2.1 Power and Ground Pins

For clean on-chip power distribution, the processor has 181 V

(power) and 185 V

(ground)

inputs. All V

pins must be connected to the processor power plane, while all V

pins must be

connected to the system ground plane. The processor V

pins must be supplied with the voltage

determined by the processor Voltage IDentification (VID) pins.

Eleven signals are denoted as V

, which provide termination for the front side bus and power to

the I/O buffers. The platform must implement a separate supply for these pins, which meets the V

specifications outlined in Table 9.

2.2 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the Intel® Xeon™ processor

with 800 MHz system bus is capable of generating large average current swings between low and

full power states. This may cause voltages on power planes to sag below their minimum values if

bulk decoupling is not adequate. Larger bulk storage (C

BULK

), such as electrolytic or aluminum-

polymer capacitors, supply current during longer lasting changes in current demand by the

component, such as coming out of an idle condition. Similarly, they act as a storage well for current

when entering an idle condition from a running condition. Care must be taken in the baseboard

design to ensure that the voltage provided to the processor remains within the specifications listed

in Table 9. Failure to do so can result in timing violations or reduced lifetime of the component.

2.2.1 V

Decoupling

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and the baseboard designer must assure a low interconnect resistance from the voltage regulator

(VRD or VRM pins) to the mPGA604 socket. The power delivery solution must insure the voltage

and current specifications are met (defined in Table 9).

2.2.2 V

Decoupling

Decoupling must be provided on the baseboard. Decoupling solutions must be sized to meet the

expected load. To insure optimal performance, various factors associated with the power delivery

solution must be considered including regulator type, power plane and trace sizing, and component

placement. A conservative decoupling solution would consist of a combination of low ESR bulk

capacitors and high frequency ceramic capacitors.

2.2.3 Front Side Bus AGTL+ Decoupling

The Intel® Xeon™ processor with 800 MHz system bus integrates signal termination on the die, as

well as part of the required high frequency decoupling capacitance on the processor package.

However, additional high frequency capacitance must be added to the baseboard to properly

decouple the return currents from the front side bus. Bulk decoupling must also be provided by the

baseboard for proper AGTL+ bus operation.

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Fujitsu P4X-0036-2M-800L Datasheet Page 13

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