Fujitsu P4X-0036-2M-800L Datasheet download pdf (Page 76)

Intel® Xeon™ Processor with 800 MHz System Bus

76 Datasheet

7.2.1 Normal State

This is the normal operating state for the processor.

7.2.2 HALT Power-Down State

HALT is a low power state entered when all logical processors have executed the HALT or

MWAIT instruction. When one of the logical processors executes the HALT or MWAIT

instruction, that logical processor is halted; however, the other processor continues normal

operation. The processor will transition to the Normal state upon the occurrence of SMI#, BINIT#,

INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front side bus. RESET# will

cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the HALT Power Down state. See the IA-32 Intel® Architecture Software Developer's Manual,

Volume III: System Programming Guide for more information.

The system can generate a STPCLK# while the processor is in the HALT Power Down state. When

the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.

While in HALT Power Down state, the processor will process front side bus snoops and interrupts.

7.2.3 Stop-Grant State

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued

° Acknowledge special bus cycle. Once the

STPCLK# pin has been asserted, it may only be deasserted once the processor is in the

° state. For

the Intel® Xeon™ processor with 800 MHz system bus, both logical processors must be in the

state before the deassertion of STPCLK#.

Figure 15. Stop Clock State Machine

CS00268

HALT Snoop State

BCLK running

Service snoops to caches

HALT State

BCLK running

Snoops and interrupts allowed

Normal State

Normal execution

Stop-Grant State

BCLK running

Service and interrupts allowed

Stop-Grant Snoop State

BCLK running

Service snoops to caches

Snoop

Event

Occurs

Snoop

Event

Ser vi ced

STPCLK#

Asser ted

STPCLK#

Deasserted

HALT or MWAIT Instruction and

HALT Bus Cycle Gener ated

INIT#, BINIT#, INTR, NMI, SMI#,

RESET#, FSB Inter rupt s

Snoop Event Occurs

Snoop Event Serviced

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 95 96

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Fujitsu P4X-0036-2M-800L Datasheet Page 76

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