Fujitsu P4X-0036-2M-800L Datasheet download pdf (Page 44)

Intel® Xeon™ Processor with 800 MHz System Bus

44 Datasheet

LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front side bus

agents. When the APIC functionality is disabled, the LINT0/INTR signal becomes INTR,

a maskable interrupt request signal, and LINT1/NMI becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those names on the

Pentium® processor. Both signals are asynchronous.

These signals must be software configured via BIOS programming of the APIC register

space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by

default after Reset, operation of these pins as LINT[1:0] is the default configuration.

LOCK# I/O LOCK# indicates to the system that a transaction must occur atomically. This signal must

connect the appropriate pins of all processor front side bus agents. For a locked

sequence of transactions, LOCK# is asserted from the beginning of the first transaction

to the end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the processor front

side bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents

to retain ownership of the processor front side bus throughout the bus locked operation

and ensure the atomicity of lock.

MCERR# I/O MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error without a

bus protocol violation. It may be driven by all processor front side bus agents.

MCERR# assertion conditions are configurable at a system level. Assertion options are

defined by the following options:

• Enabled or disabled.

• Asserted, if configured, for internal errors along with IERR#.

• Asserted, if configured, by the request initiator of a bus transaction after it observes

an error.

• Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32 Software

Developer’s Manual, Volume 3: System Programming Guide.

Since multiple agents may drive this signal at the same time, MCERR# is a wired-OR

signal which must connect the appropriate pins of all processor front side bus agents. In

order to avoid wired-OR glitches associated with simultaneous edge transitions driven by

multiple drivers, MCERR# is activated on specific clock edges and sampled on specific

clock edges.

ODTEN I ODTEN (On-die termination enable) should be connected to V

to enable on-die

termination for end bus agents. For middle bus agents, pull this signal down via a resistor

to ground to disable on-die termination. Whenever ODTEN is high, on-die termination will

be active, regardless of other states of the bus.

OPTIMIZED/

COMPAT#

I This is an input pin to the processor to determine if the processor is in an optimized

platform or a compatible platform. This signal does includes a weak on-die pull-up to V

PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor temperature monitoring

sensor detects that the processor die temperature has reached its factory configured trip

point. This indicates that the processor Thermal Control Circuit (TCC) has been

activated, if enabled. See Section 6.2.3 for more details.

PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean

indication that all processor clocks and power supplies are stable and within their

specifications. “Clean” implies that the signal will remain low (capable of sinking leakage

current), without glitches, from the time that the power supplies are turned on until they

come within specification. The signal must then transition monotonically to a high state.

PWRGOOD can be driven inactive at any time, but clocks and power must again be

stable before a subsequent rising edge of PWRGOOD. It must also meet the minimum

pulse width specification in Table 15, and be followed by a 1-10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect internal

circuits against voltage sequencing issues. It should be driven high throughout boundary

scan operation.

Table 20. Signal Definitions (Sheet 6 of 9)

Name Type Description Notes

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 95 96

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Fujitsu P4X-0036-2M-800L Datasheet Page 44

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